Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8986d2f5 authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
Browse files

[MIPS] cevt-txx9: Reset timer counter on initialization 



The txx9_tmr_init() will not clear a timer counter register in a certain
case.  The counter register is cleared on 1->0 transition of TCE bit if
CRE=1.  So just clearing the TCE bit is not enough.

Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 7e3297dc

arch/mips/kernel/cevt-txx9.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr) 
	struct txx9_tmr_reg __iomem *tmrptr;

	struct txx9_tmr_reg __iomem *tmrptr;





	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));

	/* Start once to make CounterResetEnable effective */

	__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);

	/* Stop and reset the counter */

	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);

	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);

	__raw_writel(0, &tmrptr->tisr);

	__raw_writel(0, &tmrptr->tisr);

	__raw_writel(0xffffffff, &tmrptr->cpra);

	__raw_writel(0xffffffff, &tmrptr->cpra);