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Commit 8980aa3c authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Only program watermark for full update. 



For scaling and position change, it isn't necessary to program
watermark and check P-State as well.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f97da580

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −3
Original line number Diff line number Diff line
@@ -1178,9 +1178,7 @@ static void commit_planes_for_stream(struct dc *dc, 
	if (update_type == UPDATE_TYPE_FULL) {

		dc->hwss.set_bandwidth(dc, context, false);

		context_clock_trace(dc, context);

	}



	if (update_type > UPDATE_TYPE_FAST) {

		for (j = 0; j < dc->res_pool->pipe_count; j++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
@@ -1215,7 +1213,7 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



	if (update_type > UPDATE_TYPE_FAST)

	if (update_type == UPDATE_TYPE_FULL)

		context_timing_trace(dc, &context->res_ctx);



	/* Perform requested Updates */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

+3 −0
Original line number Diff line number Diff line
@@ -651,6 +651,8 @@ void dpp1_dscl_set_scaler_manual_scale( 
	if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

		return;



	PERF_TRACE();



	dpp->scl_data = *scl_data;



	/* Recout */
@@ -704,4 +706,5 @@ void dpp1_dscl_set_scaler_manual_scale( 
		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);



	dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);

	PERF_TRACE();

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+19 −27
Original line number Diff line number Diff line
@@ -2056,11 +2056,6 @@ static void program_all_pipe_in_tree( 
{

	if (pipe_ctx->top_pipe == NULL) {



		if (dc->debug.sanity_checks) {

			/* pstate stuck check after watermark update */

			dcn10_verify_allow_pstate_change_high(dc);

		}



		pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;

		pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;

		pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
@@ -2094,11 +2089,6 @@ static void program_all_pipe_in_tree( 
			dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

	}



	if (dc->debug.sanity_checks) {

		/* pstate stuck check after each pipe is programmed */

		dcn10_verify_allow_pstate_change_high(dc);

	}



	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)

		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);

}
@@ -2183,6 +2173,7 @@ static void dcn10_apply_ctx_for_surface( 
	struct timing_generator *tg;

	bool removed_pipe[4] = { false };

	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;

	bool program_water_mark = false;



	struct pipe_ctx *top_pipe_to_program =

			find_top_pipe_for_stream(dc, context, stream);
@@ -2192,9 +2183,6 @@ static void dcn10_apply_ctx_for_surface( 


	tg = top_pipe_to_program->stream_res.tg;



	if (dc->debug.sanity_checks)

		dcn10_verify_allow_pstate_change_high(dc);



	tg->funcs->lock(tg);



	if (num_planes == 0) {
@@ -2261,11 +2249,18 @@ static void dcn10_apply_ctx_for_surface( 
	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *old_pipe_ctx =

				&dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];



		if (pipe_ctx->stream == stream &&

				pipe_ctx->plane_state &&

			pipe_ctx->plane_state->update_flags.bits.full_update)

			program_water_mark = true;



		if (removed_pipe[i] && num_planes == 0)

			dcn10_disable_plane(dc, old_pipe_ctx);

	}



	if (program_water_mark) {

		if (dc->debug.sanity_checks) {

			/* pstate stuck check after watermark update */

			dcn10_verify_allow_pstate_change_high(dc);
@@ -2278,7 +2273,7 @@ static void dcn10_apply_ctx_for_surface( 
			/* pstate stuck check after watermark update */

			dcn10_verify_allow_pstate_change_high(dc);

		}



	}

/*	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,

			"\n============== Watermark parameters ==============\n"

			"a.urgent_ns: %d \n"
@@ -2326,9 +2321,6 @@ static void dcn10_apply_ctx_for_surface( 
			context->bw.dcn.watermarks.d.pte_meta_urgent_ns

			);

*/



	if (dc->debug.sanity_checks)

		dcn10_verify_allow_pstate_change_high(dc);

}



static void dcn10_set_bandwidth(