Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 894116bd authored by Aida Mynzhasova's avatar Aida Mynzhasova Committed by David S. Miller
Browse files

powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file 



Currently IEEE 1588 timer reference clock source is determined through
hard-coded value in gianfar_ptp driver. This patch allows to select ptp
clock source by means of device tree file node.

For instance:

	fsl,cksel = <0>;

for using external (TSEC_TMR_CLK input) high precision timer
reference clock.

Other acceptable values:

	<1> : eTSEC system clock
	<2> : eTSEC1 transmit clock
	<3> : RTC clock input

When this attribute isn't used, eTSEC system clock will serve as
IEEE 1588 timer reference clock.

Signed-off-by: default avatarAida Mynzhasova <aida.mynzhasova@skitlab.ru>
Acked-by: default avatarRichard Cochran <richardcochran@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 559835ea

Documentation/devicetree/bindings/net/fsl-tsec-phy.txt

+15 −1
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ General Properties: 


Clock Properties:



  - fsl,cksel        Timer reference clock source.

  - fsl,tclk-period  Timer reference clock period in nanoseconds.

  - fsl,tmr-prsc     Prescaler, divides the output clock.

  - fsl,tmr-add      Frequency compensation value.
@@ -97,7 +98,7 @@ Clock Properties: 
  clock. You must choose these carefully for the clock to work right.

  Here is how to figure good values:



  TimerOsc     = system clock               MHz

  TimerOsc     = selected reference clock   MHz

  tclk_period  = desired clock period       nanoseconds

  NominalFreq  = 1000 / tclk_period         MHz

  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
@@ -114,6 +115,18 @@ Clock Properties: 
  Pulse Per Second (PPS) signal, since this will be offered to the PPS

  subsystem to synchronize the Linux clock.



  "fsl,cksel" property allows to select different reference clock

  sources:



  <0> - external high precision timer reference clock (TSEC_TMR_CLK

        input is used for this purpose);

  <1> - eTSEC system clock;

  <2> - eTSEC1 transmit clock;

  <3> - RTC clock input.



  When this attribute is not used, eTSEC system clock will serve as

  IEEE 1588 timer reference clock.



Example:



	ptp_clock@24E00 {
@@ -121,6 +134,7 @@ Example: 
		reg = <0x24E00 0xB0>;

		interrupts = <12 0x8 13 0x8>;

		interrupt-parent = < &ipic >;

		fsl,cksel       = <1>;

		fsl,tclk-period = <10>;

		fsl,tmr-prsc    = <100>;

		fsl,tmr-add     = <0x999999A4>;

drivers/net/ethernet/freescale/gianfar_ptp.c

+3 −1
Original line number Diff line number Diff line
@@ -452,6 +452,8 @@ static int gianfar_ptp_probe(struct platform_device *dev) 
	err = -ENODEV;



	etsects->caps = ptp_gianfar_caps;



	if (get_of_u32(node, "fsl,cksel", &etsects->cksel))

		etsects->cksel = DEFAULT_CKSEL;



	if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||