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Commit 89278709 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GPU PIL properties for sm6150"

parents 084dd0e5 64b47f18

arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -11,6 +11,12 @@ 
 */



&soc {

	pil_gpu: qcom,kgsl-hyp {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a608_zap";

	};



	msm_gpu: qcom,kgsl-3d0@5000000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
@@ -204,7 +210,9 @@ 
		clock-names = "iface_clk", "mem_clk", "mem_iface_clk",

				"alt_mem_iface_clk";



		qcom,secure_align_mask = <0xfff>;

		qcom,retention;

		qcom,hyp_secure_alloc;



		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";
@@ -212,5 +220,10 @@ 
			iommus = <&kgsl_smmu 0x0 0x401>;

			qcom,gpu-offset = <0xa8000>;

		};

		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_secure";

			iommus = <&kgsl_smmu 0x2 0x400>;

		};

	};

};

drivers/gpu/msm/adreno-gpulist.h

+2 −1
Original line number Diff line number Diff line
@@ -447,8 +447,9 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 0,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT,

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a608_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = (SZ_128K + SZ_4K),

		.num_protected_regs = 0x20,