irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()

A DMB instruction can be used to ensure the relative order of only
memory accesses before and after the barrier. Since writes to system
registers are not memory operations, barrier DMB is not sufficient
for observability of memory accesses that occur before ICC_SGI1R_EL1
writes.

A DSB instruction ensures that no instructions that appear in program
order after the DSB instruction, can execute until the DSB instruction
has completed.

Change-Id: I0f82760387803d016f950065a72374441f3437f9
Cc: stable@vger.kernel.org
Acked-by: Will Deacon <will.deacon@arm.com&gt;,>
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Git-commit: 21ec30c0ef5234fb1039cc7c7737d885bf875a9e
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>