x86/mce: Clear Local MCE opt-in before kexec (8838eb6c) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/x86/include/asm/mce.h

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -151,10 +151,12 @@ extern int mce_p5_enabled;
	#ifdef CONFIG_X86_MCE		#ifdef CONFIG_X86_MCE
	int mcheck_init(void);		int mcheck_init(void);
	void mcheck_cpu_init(struct cpuinfo_x86 *c);		void mcheck_cpu_init(struct cpuinfo_x86 *c);
			void mcheck_cpu_clear(struct cpuinfo_x86 *c);
	void mcheck_vendor_init_severity(void);		void mcheck_vendor_init_severity(void);
	#else		#else
	static inline int mcheck_init(void) { return 0; }		static inline int mcheck_init(void) { return 0; }
	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}		static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
			static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
	static inline void mcheck_vendor_init_severity(void) {}		static inline void mcheck_vendor_init_severity(void) {}
	#endif		#endif

	@@ -181,12 +183,14 @@ DECLARE_PER_CPU(struct device *, mce_device);

	#ifdef CONFIG_X86_MCE_INTEL		#ifdef CONFIG_X86_MCE_INTEL
	void mce_intel_feature_init(struct cpuinfo_x86 *c);		void mce_intel_feature_init(struct cpuinfo_x86 *c);
			void mce_intel_feature_clear(struct cpuinfo_x86 *c);
	void cmci_clear(void);		void cmci_clear(void);
	void cmci_reenable(void);		void cmci_reenable(void);
	void cmci_rediscover(void);		void cmci_rediscover(void);
	void cmci_recheck(void);		void cmci_recheck(void);
	#else		#else
	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }		static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
			static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
	static inline void cmci_clear(void) {}		static inline void cmci_clear(void) {}
	static inline void cmci_reenable(void) {}		static inline void cmci_reenable(void) {}
	static inline void cmci_rediscover(void) {}		static inline void cmci_rediscover(void) {}

arch/x86/kernel/cpu/mcheck/mce.c

+30 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1606,6 +1606,17 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
	}		}
	}		}

			static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
			{
			switch (c->x86_vendor) {
			case X86_VENDOR_INTEL:
			mce_intel_feature_clear(c);
			break;
			default:
			break;
			}
			}

	static void mce_start_timer(unsigned int cpu, struct timer_list *t)		static void mce_start_timer(unsigned int cpu, struct timer_list *t)
	{		{
	unsigned long iv = check_interval * HZ;		unsigned long iv = check_interval * HZ;
	@@ -1672,6 +1683,25 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
	__mcheck_cpu_init_timer();		__mcheck_cpu_init_timer();
	}		}

			/*
			* Called for each booted CPU to clear some machine checks opt-ins
			*/
			void mcheck_cpu_clear(struct cpuinfo_x86 *c)
			{
			if (mca_cfg.disabled)
			return;

			if (!mce_available(c))
			return;

			/*
			* Possibly to clear general settings generic to x86
			* __mcheck_cpu_clear_generic(c);
			*/
			__mcheck_cpu_clear_vendor(c);

			}

	/*		/*
	* mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.		* mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
	*/		*/

arch/x86/kernel/cpu/mcheck/mce_intel.c

+18 −1

Original line number	Original line	Diff line number	Diff line
	@@ -434,7 +434,7 @@ static void intel_init_cmci(void)
	cmci_recheck();		cmci_recheck();
	}		}

	void intel_init_lmce(void)		static void intel_init_lmce(void)
	{		{
	u64 val;		u64 val;

	@@ -447,9 +447,26 @@ void intel_init_lmce(void)
	wrmsrl(MSR_IA32_MCG_EXT_CTL, val \| MCG_EXT_CTL_LMCE_EN);		wrmsrl(MSR_IA32_MCG_EXT_CTL, val \| MCG_EXT_CTL_LMCE_EN);
	}		}

			static void intel_clear_lmce(void)
			{
			u64 val;

			if (!lmce_supported())
			return;

			rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
			val &= ~MCG_EXT_CTL_LMCE_EN;
			wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
			}

	void mce_intel_feature_init(struct cpuinfo_x86 *c)		void mce_intel_feature_init(struct cpuinfo_x86 *c)
	{		{
	intel_init_thermal(c);		intel_init_thermal(c);
	intel_init_cmci();		intel_init_cmci();
	intel_init_lmce();		intel_init_lmce();
	}		}

			void mce_intel_feature_clear(struct cpuinfo_x86 *c)
			{
			intel_clear_lmce();
			}

arch/x86/kernel/process.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -29,6 +29,7 @@
	#include <asm/debugreg.h>		#include <asm/debugreg.h>
	#include <asm/nmi.h>		#include <asm/nmi.h>
	#include <asm/tlbflush.h>		#include <asm/tlbflush.h>
			#include <asm/mce.h>

	/*		/*
	* per-CPU TSS segments. Threads are completely 'soft' on Linux,		* per-CPU TSS segments. Threads are completely 'soft' on Linux,
	@@ -319,6 +320,7 @@ void stop_this_cpu(void *dummy)
	*/		*/
	set_cpu_online(smp_processor_id(), false);		set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();		disable_local_APIC();
			mcheck_cpu_clear(this_cpu_ptr(&cpu_info));

	for (;;)		for (;;)
	halt();		halt();

arch/x86/kernel/smp.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -30,6 +30,7 @@
	#include <asm/proto.h>		#include <asm/proto.h>
	#include <asm/apic.h>		#include <asm/apic.h>
	#include <asm/nmi.h>		#include <asm/nmi.h>
			#include <asm/mce.h>
	#include <asm/trace/irq_vectors.h>		#include <asm/trace/irq_vectors.h>
	/*		/*
	* Some notes on x86 processor bugs affecting SMP operation:		* Some notes on x86 processor bugs affecting SMP operation:
	@@ -243,6 +244,7 @@ static void native_stop_other_cpus(int wait)
	finish:		finish:
	local_irq_save(flags);		local_irq_save(flags);
	disable_local_APIC();		disable_local_APIC();
			mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
	local_irq_restore(flags);		local_irq_restore(flags);
	}		}