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Commit 876ccfa9 authored by Da Hoon Pyun's avatar Da Hoon Pyun
Browse files

msm: npu: Limit maximum NPU frequency based on the efuse value 



There are different maximum NPU frequencies on each device which
are indicated by the efuse value. This change is to apply this
limitation based on the efuse value.

Change-Id: I92d0f39b9d30496f12d3f3d5dbc3a3515af90bf6
Signed-off-by: default avatarDa Hoon Pyun <dpyun@codeaurora.org>
parent ab2a8e25

drivers/media/platform/msm/npu_v2/npu_dev.c

+29 −8
Original line number Diff line number Diff line 
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1815,17 +1815,20 @@ static int npu_of_parse_pwrlevels(struct npu_device *npu_dev, 


	/* Read FMAX info if available */

	if (npu_dev->qfprom_io.base) {

		fmax = (npu_qfprom_reg_read(npu_dev,

			QFPROM_FMAX_REG_OFFSET) & QFPROM_FMAX_BITS_MASK) >>

			QFPROM_FMAX_BITS_SHIFT;

		fmax = ((npu_qfprom_reg_read(npu_dev,

			QFPROM_FMAX_REG_OFFSET_1) & QFPROM_FMAX_BITS_MASK_1) >>

			QFPROM_FMAX_BITS_SHIFT_1) +

			((npu_qfprom_reg_read(npu_dev,

			QFPROM_FMAX_REG_OFFSET_2) & QFPROM_FMAX_BITS_MASK_2) <<

			QFPROM_FMAX_BITS_SHIFT_2);



		NPU_DBG("fmax %x\n", fmax);



		switch (fmax) {

		case 1:

		case 2:

			fmax_pwrlvl = NPU_PWRLEVEL_NOM;

		case 0x1F:

			fmax_pwrlvl = NPU_PWRLEVEL_SVS;

			break;

		case 3:

		case 0x29:

			fmax_pwrlvl = NPU_PWRLEVEL_SVS_L1;

			break;

		default:
@@ -2319,6 +2322,24 @@ static int npu_probe(struct platform_device *pdev) 
	NPU_DBG("apss_shared phy address=0x%llx virt=%pK\n",

		res->start, npu_dev->apss_shared_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "qfprom_physical");

	if (!res) {

		NPU_INFO("unable to get qfprom_physical resource\n");

	} else {

		npu_dev->qfprom_io.size = resource_size(res);

		npu_dev->qfprom_io.phy_addr = res->start;

		npu_dev->qfprom_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->qfprom_io.size);

		if (unlikely(!npu_dev->qfprom_io.base)) {

			NPU_ERR("unable to map qfprom_physical\n");

			rc = -ENOMEM;

			goto error_get_dev_num;

		}

		NPU_DBG("qfprom_physical phy address=0x%llx virt=%pK\n",

			res->start, npu_dev->qfprom_io.base);

	}



	rc = npu_parse_dt_regulator(npu_dev);

	if (rc)

		goto error_get_dev_num;

drivers/media/platform/msm/npu_v2/npu_hw_access.h

+9 −4
Original line number Diff line number Diff line 
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -26,9 +26,14 @@ 
#define IPC_MEM_OFFSET_FROM_SSTCM 0x00018000

#define SYS_CACHE_SCID 23



#define QFPROM_FMAX_REG_OFFSET 0x000001C8

#define QFPROM_FMAX_BITS_MASK  0x0000000C

#define QFPROM_FMAX_BITS_SHIFT 2

#define QFPROM_FMAX_REG_OFFSET_1 0x00006014

#define QFPROM_FMAX_BITS_MASK_1  0xF8000000

#define QFPROM_FMAX_BITS_SHIFT_1 27



#define QFPROM_FMAX_REG_OFFSET_2 0x00006018

#define QFPROM_FMAX_BITS_MASK_2  0x00000007

#define QFPROM_FMAX_BITS_SHIFT_2 5





#define REGW(npu_dev, off, val) npu_core_reg_write(npu_dev, off, val)

#define REGR(npu_dev, off) npu_core_reg_read(npu_dev, off)