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Commit 86c2d44d authored by Diptanshu Jamgade's avatar Diptanshu Jamgade
Browse files

ARM: dts: msm: Update the clock controller and GDSC nodes for ATOLL 



Update the RPMHCC, GCC, GPUCC, VIDEOCC, DIPSCC, NPUCC, MCCC, CPUCC
and DEBUGCC clock controller device nodes to register the actual
clock controller drivers. Also, update the ATOLL GDSCs by replacing
the dummy nodes with actual GDSC regulator driver.

Change-Id: Ie888e0bc73004a05df79bfa51862db55e0570fb9
Signed-off-by: default avatarDiptanshu Jamgade <djamgade@codeaurora.org>
parent 29444f60

arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi

+15 −15
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
&soc {

	/* GDSCs in Global CC */

	ufs_phy_gdsc: qcom,gdsc@177004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ufs_phy_gdsc";

		reg = <0x177004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -22,7 +22,7 @@ 
	};



	usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "usb30_prim_gdsc";

		reg = <0x10f004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -30,7 +30,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		reg = <0x17d040 0x4>;

		qcom,no-status-check-on-disable;
@@ -39,7 +39,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

		reg = <0x17d044 0x4>;

		qcom,no-status-check-on-disable;
@@ -49,7 +49,7 @@ 


	/* GDSCs in Camera CC */

	bps_gdsc: qcom,gdsc@ad06004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "bps_gdsc";

		reg = <0xad06004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -57,7 +57,7 @@ 
	};



	ipe_0_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ipe_0_gdsc";

		reg = <0xad07004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -65,7 +65,7 @@ 
	};



	ife_0_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ife_0_gdsc";

		reg = <0xad09004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -73,7 +73,7 @@ 
	};



	ife_1_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ife_1_gdsc";

		reg = <0xad0a004 0x4>;

		qcom,poll-cfg-gdscr;
@@ -81,7 +81,7 @@ 
	};



	titan_top_gdsc: qcom,gdsc@ad0b134 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "titan_top_gdsc";

		reg = <0xad0b134 0x4>;

		qcom,poll-cfg-gdscr;
@@ -90,7 +90,7 @@ 


	/* GDSCs in Display CC */

	mdss_core_gdsc: qcom,gdsc@af03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mdss_core_gdsc";

		reg = <0xaf03000 0x4>;

		qcom,poll-cfg-gdscr;
@@ -117,7 +117,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@509106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x509106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -128,7 +128,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@509100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x509100c 0x4>;

		qcom,poll-cfg-gdscr;
@@ -139,14 +139,14 @@ 


	/* GDSCs in Video CC */

	vcodec0_gdsc: qcom,gdsc@ab00874 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "vcodec0_gdsc";

		reg = <0xab00874 0x4>;

		status = "disabled";

	};



	venus_gdsc: qcom,gdsc@ab00814 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "venus_gdsc";

		reg = <0xab00814 0x4>;

		status = "disabled";
@@ -154,7 +154,7 @@ 


	/* GDSCs in NPU CC */

	npu_core_gdsc: qcom,gdsc@9981004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "npu_core_gdsc";

		reg = <0x9981004 0x4>;

		status = "disabled";

arch/arm64/boot/dts/qcom/atoll.dtsi

+81 −23
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
#include <dt-bindings/clock/qcom,cpucc-sm8150.h>

#include <dt-bindings/clock/qcom,dispcc-atoll.h>

#include <dt-bindings/clock/qcom,gcc-atoll.h>

#include <dt-bindings/clock/qcom,gpucc-atoll.h>

#include <dt-bindings/clock/qcom,gpucc-sdmmagpie.h>

#include <dt-bindings/clock/qcom,npucc-atoll.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-atoll.h>
@@ -1563,56 +1563,88 @@ 
		};

	};



	clocks {

		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			clock-output-names = "chip_sleep_clk";

			#clock-cells = <1>;

		};

	};



	clock_rpmh: qcom,rpmh {

		compatible = "qcom,dummycc";

		clock-output-names = "rpm_clocks";

		compatible = "qcom,rpmh-clk-atoll";

		mboxes = <&apps_rsc 0>;

		mbox-names = "apps";

		#clock-cells = <1>;

	};



	clock_aop: qcom,aopclk {

		compatible = "qcom,dummycc";

		clock-output-names = "aop_clocks";

		compatible = "qcom,aop-qmp-clk";

		#clock-cells = <1>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

	clock_gcc: qcom,gcc@100000 {

		compatible = "qcom,atoll-gcc", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_camcc: qcom,camcc {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

	clock_camcc: qcom,camcc@ad00000 {

		compatible = "qcom,atoll-camcc", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

	clock_dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,atoll-dispcc", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gpucc: qcom,gpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

	clock_gpucc: qcom,gpucc@5090000 {

		compatible = "qcom,atoll-gpucc", "syscon";

		reg = <0x5090000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_gfx-supply = <&VDD_GFX_LEVEL>;

		qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;

		qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_npucc: qcom,npucc {

		compatible = "qcom,dummycc";

		clock-output-names = "npucc_clocks";

	clock_npucc: qcom,npucc@9980000 {

		compatible = "qcom,atoll-npucc", "syscon";

		reg = <0x9980000 0x10000>,

			<0x9800000 0x10000>,

			<0x9810000 0x10000>;

		reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";

		npu_gdsc-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_videocc: qcom,videocc {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

	clock_videocc: qcom,videocc@ab00000 {

		compatible = "qcom,atoll-videocc", "syscon";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1628,6 +1660,32 @@ 
		status = "disabled";

	};



	cpucc_debug: syscon@182a0018 {

		compatible = "syscon";

		reg = <0x182a0018 0x4>;

	};



	mccc_debug: syscon@90b0000 {

		compatible = "syscon";

		reg = <0x090b0000 0x100>;

	};



	clock_debug: qcom,cc-debug {

		compatible = "qcom,atoll-debugcc";

		qcom,cc-count = <8>;

		qcom,gcc = <&clock_gcc>;

		qcom,gpucc = <&clock_gpucc>;

		qcom,camcc = <&clock_camcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		qcom,cpucc = <&cpucc_debug>;

		qcom,mccc = <&mccc_debug>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "xo_clk_src";

		#clock-cells = <1>;

	};



	tcsr_mutex_block: syscon@01F40000 {

		compatible = "syscon";

		reg = <0x01F40000 0x20000>;