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Commit 86bf265a authored by Krishna Manikandan's avatar Krishna Manikandan
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ARM: dts: msm: enable rscc for atoll target



Add necessary support to enable rscc for
atoll target.

Change-Id: I7bdd281701279a161d245b40445bd5c639514016
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent 48d84bd1
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+1 −1
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@
};

&mdss_mdp {
	connectors = <&sde_wb &sde_dsi &sde_dp>;
	connectors = <&sde_wb &sde_dsi &sde_dp &sde_rscc>;
};

&dsi_rm69299_visionox_amoled_video {
+0 −17
Original line number Diff line number Diff line
@@ -40,8 +40,6 @@
		clock-max-rate = <0 0 0 460000000 19200000 460000000
						460000000>;

		sde-vdd-supply = <&mdss_core_gdsc>;

		/* interrupt config */
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
@@ -234,20 +232,6 @@
			qcom,sde-dspp-dither = <0x82c 0x00010007>;
		};

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

		qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "sde-vdd";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};

		smmu_sde_sec: qcom,smmu_sde_sec_cb {
			compatible = "qcom,smmu_sde_sec";
			iommus = <&apps_smmu 0x801 0x0>;
@@ -283,7 +267,6 @@
			<0xaf30000 0x3fd4>;
		reg-names = "drv", "wrapper";
		qcom,sde-rsc-version = <3>;
		status = "disabled";

		qcom,sde-dram-channels = <2>;