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Commit 8671b74e authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
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drm/msm/dsi-staging: add support to set continuous clock through phy 



Adds support to configure DSI controller and phy to force the clock
lane to HS mode always for phy ver 4.0.

Change-Id: Ie49f1b3f2239adcf7113189e7159bcbbb1c8ab14
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent d9f6c79d

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, 
	ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk;

	ctrl->ops.wait4dynamic_refresh_done =

		dsi_ctrl_hw_cmn_wait4dynamic_refresh_done;

	ctrl->ops.hs_req_sel = dsi_ctrl_hw_cmn_hs_req_sel;



	switch (version) {

	case DSI_CTRL_VERSION_1_4:
@@ -271,6 +272,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) 
	phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;

	phy->ops.reset_clk_en_sel = dsi_phy_hw_v4_0_reset_clk_en_sel;

	phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;

}



/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg, 
int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);
@@ -256,6 +257,7 @@ void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable, 
		enum dsi_clk_gate_type clk_selection);



void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable);

void dsi_ctrl_hw_cmn_hs_req_sel(struct dsi_ctrl_hw *ctrl, bool sel_phy);



/* dynamic refresh specific functions */

void dsi_phy_hw_v3_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+10 −0
Original line number Diff line number Diff line
@@ -2757,6 +2757,16 @@ void dsi_ctrl_isr_configure(struct dsi_ctrl *dsi_ctrl, bool enable) 
	mutex_unlock(&dsi_ctrl->ctrl_lock);

}



void dsi_ctrl_hs_req_sel(struct dsi_ctrl *dsi_ctrl, bool sel_phy)

{

	if (!dsi_ctrl)

		return;



	mutex_lock(&dsi_ctrl->ctrl_lock);

	dsi_ctrl->hw.ops.hs_req_sel(&dsi_ctrl->hw, sel_phy);

	mutex_unlock(&dsi_ctrl->ctrl_lock);

}



void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable)

{

	if (!dsi_ctrl)

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+8 −0
Original line number Diff line number Diff line
@@ -817,6 +817,14 @@ int dsi_ctrl_update_host_state(struct dsi_ctrl *dsi_ctrl, 
 */

int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format);



/**

 * dsi_ctrl_hs_req_sel() - API to enable continuous clk support through phy

 * @dsi_ctrl:			DSI controller handle.

 * @sel_phy:			Boolean to control whether to select phy or

 *				controller

 */

void dsi_ctrl_hs_req_sel(struct dsi_ctrl *dsi_ctrl, bool sel_phy);



/**

 * dsi_ctrl_set_continuous_clk() - API to set/unset force clock lane HS request.

 * @dsi_ctrl:                      DSI controller handle.

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h

+7 −0
Original line number Diff line number Diff line
@@ -835,6 +835,13 @@ struct dsi_ctrl_hw_ops { 
	 * @ctrl:         Pointer to the controller host hardware.

	 */

	int (*wait4dynamic_refresh_done)(struct dsi_ctrl_hw *ctrl);



	/**

	 * hw.ops.hs_req_sel() - enable continuous clk support through phy

	 * @ctrl:	Pointer to the controller host hardware.

	 * @sel_phy:	Bool to control whether to select phy or controller

	 */

	void (*hs_req_sel)(struct dsi_ctrl_hw *ctrl, bool sel_phy);

};



/*