Loading sound/soc/mxs/mxs-saif.c +17 −5 Original line number Original line Diff line number Diff line Loading @@ -494,6 +494,7 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); struct mxs_saif *master_saif; struct mxs_saif *master_saif; u32 delay; u32 delay; int ret; master_saif = mxs_saif_get_master(saif); master_saif = mxs_saif_get_master(saif); if (!master_saif) if (!master_saif) Loading @@ -508,21 +509,32 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, dev_dbg(cpu_dai->dev, "start\n"); dev_dbg(cpu_dai->dev, "start\n"); clk_enable(master_saif->clk); ret = clk_enable(master_saif->clk); if (!master_saif->mclk_in_use) if (ret) { __raw_writel(BM_SAIF_CTRL_RUN, dev_err(saif->dev, "Failed to enable master clock\n"); master_saif->base + SAIF_CTRL + MXS_SET_ADDR); return ret; } /* /* * If the saif's master is not himself, we also need to enable * If the saif's master is not himself, we also need to enable * itself clk for its internal basic logic to work. * itself clk for its internal basic logic to work. */ */ if (saif != master_saif) { if (saif != master_saif) { clk_enable(saif->clk); ret = clk_enable(saif->clk); if (ret) { dev_err(saif->dev, "Failed to enable master clock\n"); clk_disable(master_saif->clk); return ret; } __raw_writel(BM_SAIF_CTRL_RUN, __raw_writel(BM_SAIF_CTRL_RUN, saif->base + SAIF_CTRL + MXS_SET_ADDR); saif->base + SAIF_CTRL + MXS_SET_ADDR); } } if (!master_saif->mclk_in_use) __raw_writel(BM_SAIF_CTRL_RUN, master_saif->base + SAIF_CTRL + MXS_SET_ADDR); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /* /* * write data to saif data register to trigger * write data to saif data register to trigger Loading Loading
sound/soc/mxs/mxs-saif.c +17 −5 Original line number Original line Diff line number Diff line Loading @@ -494,6 +494,7 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); struct mxs_saif *master_saif; struct mxs_saif *master_saif; u32 delay; u32 delay; int ret; master_saif = mxs_saif_get_master(saif); master_saif = mxs_saif_get_master(saif); if (!master_saif) if (!master_saif) Loading @@ -508,21 +509,32 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, dev_dbg(cpu_dai->dev, "start\n"); dev_dbg(cpu_dai->dev, "start\n"); clk_enable(master_saif->clk); ret = clk_enable(master_saif->clk); if (!master_saif->mclk_in_use) if (ret) { __raw_writel(BM_SAIF_CTRL_RUN, dev_err(saif->dev, "Failed to enable master clock\n"); master_saif->base + SAIF_CTRL + MXS_SET_ADDR); return ret; } /* /* * If the saif's master is not himself, we also need to enable * If the saif's master is not himself, we also need to enable * itself clk for its internal basic logic to work. * itself clk for its internal basic logic to work. */ */ if (saif != master_saif) { if (saif != master_saif) { clk_enable(saif->clk); ret = clk_enable(saif->clk); if (ret) { dev_err(saif->dev, "Failed to enable master clock\n"); clk_disable(master_saif->clk); return ret; } __raw_writel(BM_SAIF_CTRL_RUN, __raw_writel(BM_SAIF_CTRL_RUN, saif->base + SAIF_CTRL + MXS_SET_ADDR); saif->base + SAIF_CTRL + MXS_SET_ADDR); } } if (!master_saif->mclk_in_use) __raw_writel(BM_SAIF_CTRL_RUN, master_saif->base + SAIF_CTRL + MXS_SET_ADDR); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /* /* * write data to saif data register to trigger * write data to saif data register to trigger Loading