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Commit 860463ef authored by Umang Agrawal's avatar Umang Agrawal
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power: smb5: Fix AICL configuration for pmi632 



Currently, AICL rerun is disabled for pmi632 and the default AICL
step time and input collapse deglitch filter time is reconfigured
to minimum period. This in turn is restricting the AICL capability
of pmi632 for weak adapters leading to low AICL values and henceforth
low charge current. Hence, enable AICL rerun and restore the default
step time and deglitch filter time for pmi632 charger.

Change-Id: I536b99ec7c009006185467e3ddd8f0009aaad798
Signed-off-by: default avatarUmang Agrawal <uagrawal@codeaurora.org>
parent 6150c9ff

Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt

+5 −0
Original line number Diff line number Diff line
@@ -321,6 +321,11 @@ Charger specific properties: 
		4 = 1s, 5 = 2s, 6 = 4s and 7 = 8s. If not defined, wdog-snarl

		irq is disabled by default.



- qcom,adc-based-aicl

  Usage:      optional

  Value type: bool

  Definition: Boolean flag which when present enables ADC based AICL.



=============================================

Second Level Nodes - SMB5 Charger Peripherals

=============================================

drivers/power/supply/qcom/qpnp-smb5.c

+28 −21
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ struct smb_dt_props { 
	bool			no_battery;

	bool			hvdcp_disable;

	bool			hvdcp_autonomous;

	bool			adc_based_aicl;

	int			sec_charger_config;

	int			auto_recharge_soc;

	int			auto_recharge_vbat_mv;
@@ -559,6 +560,9 @@ static int smb5_parse_dt(struct smb5 *chip) 
	of_property_read_u32(node, "qcom,connector-internal-pull-kohm",

					&chg->connector_pull_up);



	chip->dt.adc_based_aicl = of_property_read_bool(node,

					"qcom,adc-based-aicl");



	/* Extract ADC channels */

	rc = smblib_get_iio_channel(chg, "mid_voltage", &chg->iio.mid_chan);

	if (rc < 0)
@@ -2070,14 +2074,17 @@ static int smb5_configure_typec(struct smb_charger *chg) 
		return rc;

	}



	if (chg->smb_version != PMI632_SUBTYPE) {

		rc = smblib_masked_write(chg, USBIN_LOAD_CFG_REG,

		USBIN_IN_COLLAPSE_GF_SEL_MASK | USBIN_AICL_STEP_TIMING_SEL_MASK,

				USBIN_IN_COLLAPSE_GF_SEL_MASK |

				USBIN_AICL_STEP_TIMING_SEL_MASK,

				0);

		if (rc < 0) {

			dev_err(chg->dev,

				"Couldn't set USBIN_LOAD_CFG_REG rc=%d\n", rc);

			return rc;

		}

	}



	/* Set CC threshold to 1.6 V in source mode */

	rc = smblib_masked_write(chg, TYPE_C_EXIT_STATE_CFG_REG,
@@ -2469,15 +2476,16 @@ static int smb5_init_hw(struct smb5 *chip) 
		return rc;



	/*

	 * AICL configuration:

	 * start from min and AICL ADC disable, and enable aicl rerun

	 * AICL configuration: enable aicl and aicl rerun and based on DT

	 * configuration enable/disable ADB based AICL and Suspend on collapse.

	 */

	if (chg->smb_version != PMI632_SUBTYPE) {

	mask = USBIN_AICL_PERIODIC_RERUN_EN_BIT | USBIN_AICL_ADC_EN_BIT

			| USBIN_AICL_EN_BIT | SUSPEND_ON_COLLAPSE_USBIN_BIT;

	val = USBIN_AICL_PERIODIC_RERUN_EN_BIT | USBIN_AICL_EN_BIT;

	if (!chip->dt.disable_suspend_on_collapse)

		val |= SUSPEND_ON_COLLAPSE_USBIN_BIT;

	if (chip->dt.adc_based_aicl)

		val |= USBIN_AICL_ADC_EN_BIT;



	rc = smblib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG,

			mask, val);
@@ -2485,7 +2493,6 @@ static int smb5_init_hw(struct smb5 *chip) 
		dev_err(chg->dev, "Couldn't config AICL rc=%d\n", rc);

		return rc;

	}

	}



	rc = smblib_write(chg, AICL_RERUN_TIME_CFG_REG,

				AICL_RERUN_TIME_12S_VAL);