Merge tag 'reset-for-4.19' of git://git.pengutronix.de/git/pza/linux into next/drivers

Qualcomm AOSS Reset Controller

======================================

This binding describes a reset-controller found on AOSS-CC (always on subsystem)

for Qualcomm SDM845 SoCs.

Required properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be:

		    "qcom,sdm845-aoss-cc"

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: must specify the base address and size of the register

	            space.

- #reset-cells:

	Usage: required

	Value type: <uint>

	Definition: must be 1; cell entry represents the reset index.

Example:

aoss_reset: reset-controller@c2a0000 {

	compatible = "qcom,sdm845-aoss-cc";

	reg = <0xc2a0000 0x31000>;

	#reset-cells = <1>;

};

Specifying reset lines connected to IP modules

==============================================

Device nodes that need access to reset lines should

specify them as a reset phandle in their corresponding node as

specified in reset.txt.

For list of all valid reset indicies see

<dt-bindings/reset/qcom,sdm845-aoss.h>

Example:

modem-pil@4080000 {

	...

	resets = <&aoss_reset AOSS_CC_MSS_RESTART>;

	reset-names = "mss_restart";

	...

};

		other nodes ...

	};

USB3 core reset

---------------

USB3 core reset belongs to USB3 glue layer. Before using the core reset,

it is necessary to control the clocks and resets to enable this layer.

These clocks and resets should be described in each property.

Required properties:

- compatible: Should be

    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC

    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC

    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC

    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC

- #reset-cells: Should be 1.

- reg: Specifies offset and length of the register set for the device.

- clocks: A list of phandles to the clock gate for USB3 glue layer.

	According to the clock-names, appropriate clocks are required.

- clock-names: Should contain

    "gio", "link" - for Pro4 SoC

    "link"        - for others

- resets: A list of phandles to the reset control for USB3 glue layer.

	According to the reset-names, appropriate resets are required.

- reset-names: Should contain

    "gio", "link" - for Pro4 SoC

    "link"        - for others

Example:

	usb-glue@65b00000 {

		compatible = "socionext,uniphier-ld20-dwc3-glue",

			     "simple-mfd";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x65b00000 0x400>;

		usb_rst: reset@0 {

			compatible = "socionext,uniphier-ld20-usb3-reset";

			reg = <0x0 0x4>;

			#reset-cells = <1>;

			clock-names = "link";

			clocks = <&sys_clk 14>;

			reset-names = "link";

			resets = <&sys_rst 14>;

		};

		regulator {

			...

		};

		phy {

			...

		};

		...

	};

	help

	  This enables the reset driver for ImgTec Pistachio SoCs.

config RESET_QCOM_AOSS

	bool "Qcom AOSS Reset Driver"

	depends on ARCH_QCOM || COMPILE_TEST

	help

	  This enables the AOSS (always on subsystem) reset driver

	  for Qualcomm SDM845 SoCs. Say Y if you want to control

	  reset signals provided by AOSS for Modem, Venus, ADSP,

	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.

config RESET_SIMPLE

	bool "Simple Reset Controller Driver" if COMPILE_TEST

	default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED

	  Say Y if you want to control reset signals provided by System Control

	  block, Media I/O block, Peripheral Block.

config RESET_UNIPHIER_USB3

	tristate "USB3 reset driver for UniPhier SoCs"

	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF

	default ARCH_UNIPHIER

	select RESET_SIMPLE

	help

	  Support for the USB3 core reset on UniPhier SoCs.

	  Say Y if you want to control reset signals provided by

	  USB3 glue layer.

config RESET_ZYNQ

	bool "ZYNQ Reset Driver" if COMPILE_TEST

	default ARCH_ZYNQ

obj-$(CONFIG_RESET_MESON) += reset-meson.o

obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o

obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o

obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o

obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o

obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o

obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o

obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o

obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o

obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o

obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o

// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2018 The Linux Foundation. All rights reserved.

 */

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/reset-controller.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/of_device.h>

#include <dt-bindings/reset/qcom,sdm845-aoss.h>

struct qcom_aoss_reset_map {

	unsigned int reg;

};

struct qcom_aoss_desc {

	const struct qcom_aoss_reset_map *resets;

	size_t num_resets;

};

struct qcom_aoss_reset_data {

	struct reset_controller_dev rcdev;

	void __iomem *base;

	const struct qcom_aoss_desc *desc;

};

static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {

	[AOSS_CC_MSS_RESTART] = {0x10000},

	[AOSS_CC_CAMSS_RESTART] = {0x11000},

	[AOSS_CC_VENUS_RESTART] = {0x12000},

	[AOSS_CC_GPU_RESTART] = {0x13000},

	[AOSS_CC_DISPSS_RESTART] = {0x14000},

	[AOSS_CC_WCSS_RESTART] = {0x20000},

	[AOSS_CC_LPASS_RESTART] = {0x30000},

};

static const struct qcom_aoss_desc sdm845_aoss_desc = {

	.resets = sdm845_aoss_resets,

	.num_resets = ARRAY_SIZE(sdm845_aoss_resets),

};

static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(

				struct reset_controller_dev *rcdev)

{

	return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);

}

static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,

				    unsigned long idx)

{

	struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);

	const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];

	writel(1, data->base + map->reg);

	/* Wait 6 32kHz sleep cycles for reset */

	usleep_range(200, 300);

	return 0;

}

static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,

				      unsigned long idx)

{

	struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);

	const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];

	writel(0, data->base + map->reg);

	/* Wait 6 32kHz sleep cycles for reset */

	usleep_range(200, 300);

	return 0;

}

static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,

					unsigned long idx)

{

	qcom_aoss_control_assert(rcdev, idx);

	return qcom_aoss_control_deassert(rcdev, idx);

}

static const struct reset_control_ops qcom_aoss_reset_ops = {

	.reset = qcom_aoss_control_reset,

	.assert = qcom_aoss_control_assert,

	.deassert = qcom_aoss_control_deassert,

};

static int qcom_aoss_reset_probe(struct platform_device *pdev)

{

	struct qcom_aoss_reset_data *data;

	struct device *dev = &pdev->dev;

	const struct qcom_aoss_desc *desc;

	struct resource *res;

	desc = of_device_get_match_data(dev);

	if (!desc)

		return -EINVAL;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);

	if (!data)

		return -ENOMEM;

	data->desc = desc;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	data->base = devm_ioremap_resource(dev, res);

	if (IS_ERR(data->base))

		return PTR_ERR(data->base);

	data->rcdev.owner = THIS_MODULE;

	data->rcdev.ops = &qcom_aoss_reset_ops;

	data->rcdev.nr_resets = desc->num_resets;

	data->rcdev.of_node = dev->of_node;

	return devm_reset_controller_register(dev, &data->rcdev);

}

static const struct of_device_id qcom_aoss_reset_of_match[] = {

	{ .compatible = "qcom,sdm845-aoss-cc", .data = &sdm845_aoss_desc },

	{}

};

static struct platform_driver qcom_aoss_reset_driver = {

	.probe = qcom_aoss_reset_probe,

	.driver  = {

		.name = "qcom_aoss_reset",

		.of_match_table = qcom_aoss_reset_of_match,

	},

};

builtin_platform_driver(qcom_aoss_reset_driver);

MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");

MODULE_LICENSE("GPL v2");