Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 858e6116 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge changes...

Merge changes I308912c5,I42804018,I948ad37e,I61346ee5,I8e90ce71,I5bdd9603,Ifc61ded2,Id26b32bb,Ie3e369be,I08f209e8,I73026a53,I08c852a0,I83b96a83,I20923658,I3374fbe4,Ieeec88ec,Ie85e7480,I9653dc7e into dev/msm-4.14-display

* changes:
  drm/msm/sde: update QSEED4 UV_PRELOAD configs
  drm/msm/sde: add qseed4 support
  disp: msm: sde: add proper null checks
  disp: msm: sde: add per_pipe_bw_high option
  drm/msm/sde: expose ubwc version through capability blob
  drm/msm/sde: fix the possible memory leak in driver catalog
  drm/msm/sde: increase Bus BW ib/ab vote during cont-splash
  drm/msm/sde: add support to handle horz and vert decimation support
  drm/msm/sde: add sui blendstage and QoS FL caps for kona
  drm/msm/sde: add CWB and LUTDMA VBIF remap setting
  drm/msm/sde: use cwb qos lut during clone mode for cwb
  msm/sde: add SID register support for offline rotator
  drm/msm: handle rsc jitter time based on rsc state
  drm/msm: update rsc_min_threshold for sde rsc hw block
  drm/msm: set sde rsc min threshold time
  drm/msm: adjust backoff time sde rsc
  drm/msm: update mode2 entry sequence for sde rsc
  drm:msm: add kona sde rsc support
parents e34fb3f9 e840a91f
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ msm_drm-$(CONFIG_DRM_MSM_MDP5) += mdp/mdp_format.o \

msm_drm-$(CONFIG_DRM_SDE_RSC) += sde_rsc.o \
	sde_rsc_hw.o \
	sde_rsc_hw_v3.o \

# use drm gpu driver only if qcom_kgsl driver not available
ifneq ($(CONFIG_QCOM_KGSL),y)
+2 −1
Original line number Diff line number Diff line
@@ -2007,7 +2007,8 @@ static int dsi_panel_parse_jitter_config(
				  &priv_info->panel_prefill_lines);
	if (rc) {
		pr_debug("panel prefill lines are not defined rc=%d\n", rc);
		priv_info->panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES;
		priv_info->panel_prefill_lines = mode->timing.v_back_porch +
			mode->timing.v_sync_width + mode->timing.v_front_porch;
	} else if (priv_info->panel_prefill_lines >=
					DSI_V_TOTAL(&mode->timing)) {
		pr_debug("invalid prefill lines config=%d setting to:%d\n",
+4 −0
Original line number Diff line number Diff line
@@ -496,6 +496,10 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms)
			sizeof(atomic_t), GFP_KERNEL);
	sde_kms->irq_obj.irq_counts = kcalloc(sde_kms->irq_obj.total_irqs,
			sizeof(atomic_t), GFP_KERNEL);
	if (!sde_kms->irq_obj.irq_cb_tbl || !sde_kms->irq_obj.enable_counts
			|| !sde_kms->irq_obj.irq_counts)
		return;

	for (i = 0; i < sde_kms->irq_obj.total_irqs; i++) {
		if (sde_kms->irq_obj.irq_cb_tbl)
			INIT_LIST_HEAD(&sde_kms->irq_obj.irq_cb_tbl[i]);
+10 −2
Original line number Diff line number Diff line
@@ -578,8 +578,8 @@ void sde_core_perf_crtc_update(struct drm_crtc *crtc,

			/* display rsc override during solver mode */
			if (kms->perf.bw_vote_mode == DISP_RSC_MODE &&
				get_sde_rsc_current_state(SDE_RSC_INDEX) ==
						SDE_RSC_CMD_STATE) {
				get_sde_rsc_current_state(SDE_RSC_INDEX) !=
						SDE_RSC_CLK_STATE) {
				/* update new bandwidth in all cases */
				if (params_changed && ((new->bw_ctl[i] !=
						old->bw_ctl[i]) ||
@@ -628,6 +628,14 @@ void sde_core_perf_crtc_update(struct drm_crtc *crtc,
			_sde_core_perf_crtc_update_bus(kms, crtc, i);
	}

	if (kms->perf.bw_vote_mode == DISP_RSC_MODE &&
	    ((get_sde_rsc_current_state(SDE_RSC_INDEX) != SDE_RSC_CLK_STATE
	      && params_changed) ||
	    (get_sde_rsc_current_state(SDE_RSC_INDEX) == SDE_RSC_CLK_STATE
	      && update_bus)))
		sde_rsc_client_trigger_vote(sde_cstate->rsc_client,
				update_bus ? true : false);

	/*
	 * Update the clock after bandwidth vote to ensure
	 * bandwidth is available before clock rate is increased.
+8 −0
Original line number Diff line number Diff line
@@ -5693,6 +5693,14 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
	if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
		sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");

	sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
	sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
				catalog->macrotile_mode);
	sde_kms_info_add_keyint(info, "UBWC highest banking bit",
				catalog->mdp[0].highest_bank_bit);
	sde_kms_info_add_keyint(info, "UBWC swizzle",
				catalog->mdp[0].ubwc_swizzle);

	if (sde_is_custom_client()) {
		/* No support for SMART_DMA_V1 yet */
		if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
Loading