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Commit 8588eafd authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "arm64: Apply Erratum 1024718 to Kryo4xx Cores"

parents e7fd0766 cf016771

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -84,6 +84,8 @@ 
#define ARM_CPU_PART_CORTEX_A53		0xD03

#define ARM_CPU_PART_CORTEX_A73		0xD09

#define ARM_CPU_PART_CORTEX_A75		0xD0A

#define ARM_CPU_PART_KRYO3S		0x803

#define ARM_CPU_PART_KRYO4S		0x803



#define APM_CPU_PART_POTENZA		0x000
@@ -104,6 +106,8 @@ 
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)

#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)

#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)

#define MIDR_KRYO3S	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3S)

#define MIDR_KRYO4S	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO4S)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -896,6 +896,8 @@ static bool cpu_has_broken_dbm(void) 
#ifdef CONFIG_ARM64_ERRATUM_1024718

		// A55 r0p0 -r1p0

		GENERIC_MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),

		GENERIC_MIDR_RANGE(MIDR_KRYO3S, 7, 12, 7, 12),

		GENERIC_MIDR_RANGE(MIDR_KRYO4S, 7, 12, 7, 12),

#endif

		{},

	};