Merge "net: stmmac: SDx55 EMAC HW configuration changes"

* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)

Required properties:

- compatible: Should be "qcom,sdxprairie-ethqos",

	For backwards compatibility: "st,spear600-gmac" is also supported.

- reg: Address and length of the register set for the device

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the STMMAC interrupts

- interrupt-names: Should contain a list of interrupt names corresponding to

	the interrupts in the interrupts property, if available.

	Valid interrupt names are:

  - "macirq" (combined signal for various interrupt events)

  - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)

  - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state)

- phy-mode: See ethernet.txt file in the same directory.

- snps,reset-gpio 	gpio number for phy reset.

- snps,reset-active-low boolean flag to indicate if phy reset is active low.

- snps,reset-delays-us  is triplet of delays

	The 1st cell is reset pre-delay in micro seconds.

	The 2nd cell is reset pulse in micro seconds.

	The 3rd cell is reset post-delay in micro seconds.

Optional properties:

- resets: Should contain a phandle to the STMMAC reset signal, if any

- reset-names: Should contain the reset signal name "stmmaceth", if a

	reset phandle is given

- max-frame-size: See ethernet.txt file in the same directory

- clocks: If present, the first clock should be the GMAC main clock and

  the second clock should be peripheral's register interface clock. Further

  clocks may be specified in derived bindings.

- clock-names: One name for each entry in the clocks property, the

  first one should be "stmmaceth" and the second one should be "pclk".

- ptp_ref: this is the PTP reference clock; in case of the PTP is available

  this clock is used for programming the Timestamp Addend Register. If not

  passed then the system clock will be used and this is fine on some

  platforms.

- tx-fifo-depth: See ethernet.txt file in the same directory

- rx-fifo-depth: See ethernet.txt file in the same directory

- snps,pbl		Programmable Burst Length (tx and rx)

- snps,txpbl		Tx Programmable Burst Length. Only for GMAC and newer.

			If set, DMA tx will use this value rather than snps,pbl.

- snps,rxpbl		Rx Programmable Burst Length. Only for GMAC and newer.

			If set, DMA rx will use this value rather than snps,pbl.

- snps,no-pbl-x8	Don't multiply the pbl/txpbl/rxpbl values by 8.

			For core rev < 3.50, don't multiply the values by 4.

- snps,aal		Address-Aligned Beats

- snps,fixed-burst	Program the DMA to use the fixed burst mode

- snps,mixed-burst	Program the DMA to use the mixed burst mode

- snps,force_thresh_dma_mode	Force DMA to use the threshold mode for

				both tx and rx

- snps,force_sf_dma_mode	Force DMA to use the Store and Forward

				mode for both tx and rx. This flag is

				ignored if force_thresh_dma_mode is set.

- snps,en-tx-lpi-clockgating	Enable gating of the MAC TX clock during

				TX low-power mode

- snps,multicast-filter-bins:	Number of multicast filter hash bins

				supported by this device instance

- snps,perfect-filter-entries:	Number of perfect filter entries supported

				by this device instance

- snps,ps-speed: port selection speed that can be passed to the core when

		 PCS is supported. For example, this is used in case of SGMII

		 and MAC2MAC connection.

- snps,tso: this enables the TSO feature otherwise it will be managed by

		 MAC HW capability register. Only for GMAC4 and newer.

- AXI BUS Mode parameters: below the list of all the parameters to program the

			   AXI register inside the DMA module:

	- snps,lpi_en: enable Low Power Interface

	- snps,xit_frm: unlock on WoL

	- snps,wr_osr_lmt: max write outstanding req. limit

	- snps,rd_osr_lmt: max read outstanding req. limit

	- snps,kbbe: do not cross 1KiB boundary.

	- snps,blen: this is a vector of supported burst length.

	- snps,fb: fixed-burst

	- snps,mb: mixed-burst

	- snps,rb: rebuild INCRx Burst

- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.

- Multiple RX Queues parameters: below the list of all the parameters to

				 configure the multiple RX queues:

	- snps,rx-queues-to-use: number of RX queues to be used in the driver

	- Choose one of these RX scheduling algorithms:

		- snps,rx-sched-sp: Strict priority

		- snps,rx-sched-wsp: Weighted Strict priority

	- For each RX queue

		- Choose one of these modes:

			- snps,dcb-algorithm: Queue to be enabled as DCB

			- snps,avb-algorithm: Queue to be enabled as AVB

		- snps,map-to-dma-channel: Channel to map

		- Specifiy specific packet routing:

			- snps,route-avcp: AV Untagged Control packets

			- snps,route-ptp: PTP Packets

			- snps,route-dcbcp: DCB Control Packets

			- snps,route-up: Untagged Packets

			- snps,route-multi-broad: Multicast & Broadcast Packets

		- snps,priority: RX queue priority (Range: 0x0 to 0xF)

- Multiple TX Queues parameters: below the list of all the parameters to

				 configure the multiple TX queues:

	- snps,tx-queues-to-use: number of TX queues to be used in the driver

	- Choose one of these TX scheduling algorithms:

		- snps,tx-sched-wrr: Weighted Round Robin

		- snps,tx-sched-wfq: Weighted Fair Queuing

		- snps,tx-sched-dwrr: Deficit Weighted Round Robin

		- snps,tx-sched-sp: Strict priority

	- For each TX queue

		- snps,weight: TX queue weight (if using a DCB weight algorithm)

		- Choose one of these modes:

			- snps,dcb-algorithm: TX queue will be working in DCB

			- snps,avb-algorithm: TX queue will be working in AVB

			  [Attention] Queue 0 is reserved for legacy traffic

			  and so no AVB is available in this queue.

		- Configure Credit Base Shaper (if AVB Mode selected):

			- snps,send_slope: enable Low Power Interface

			- snps,idle_slope: unlock on WoL

			- snps,high_credit: max write outstanding req. limit

			- snps,low_credit: max read outstanding req. limit

		- snps,priority: TX queue priority (Range: 0x0 to 0xF)

Examples:

	stmmac_axi_setup: stmmac-axi-config {

		snps,wr_osr_lmt = <0xf>;

		snps,rd_osr_lmt = <0xf>;

		snps,blen = <256 128 64 32 0 0 0>;

	};

	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <1>;

		snps,rx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

			snps,priority = <0x0>;

		};

	};

	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <2>;

		snps,tx-sched-wrr;

		queue0 {

			snps,weight = <0x10>;

			snps,dcb-algorithm;

			snps,priority = <0x0>;

		};

		queue1 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

			snps,priority = <0x1>;

		};

	};

	gmac0: ethernet@e0800000 {

		compatible = "qcom,sdxprairie-ethqos";

		reg = <0xe0800000 0x8000>;

		interrupt-parent = <&vic1>;

		interrupts = <24 23 22>;

		interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

		mac-address = [000000000000]; /* Filled in by U-Boot */

		max-frame-size = <3800>;

		phy-mode = "gmii";

		snps,multicast-filter-bins = <256>;

		snps,perfect-filter-entries = <128>;

		rx-fifo-depth = <16384>;

		tx-fifo-depth = <16384>;

		clocks = <&clock>;

		clock-names = "stmmaceth";

		snps,axi-config = <&stmmac_axi_setup>;

		mdio0 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dwmac-mdio";

			phy1: ethernet-phy@0 {

			};

		};

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

	};

obj-$(CONFIG_DWMAC_LPC18XX)	+= dwmac-lpc18xx.o

obj-$(CONFIG_DWMAC_MESON)	+= dwmac-meson.o dwmac-meson8b.o

obj-$(CONFIG_DWMAC_OXNAS)	+= dwmac-oxnas.o

obj-$(CONFIG_DWMAC_QCOM_ETHQOS)	+= dwmac-qcom-gpio.o

obj-$(CONFIG_DWMAC_QCOM_ETHQOS)	+= dwmac-qcom-ethqos.o

obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o

obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/phy.h>

#include <linux/regulator/consumer.h>

#include "stmmac.h"

#include "stmmac_platform.h"

#include "dwmac-qcom-ethqos.h"

#define RGMII_IO_MACRO_CONFIG		0x0

#define SDCC_HC_REG_DLL_CONFIG		0x4

#define SDCC_HC_REG_DDR_CONFIG		0xC

#define SDCC_HC_REG_DLL_CONFIG2		0x10

#define SDC4_STATUS			0x14

#define SDCC_USR_CTL			0x18

#define RGMII_IO_MACRO_CONFIG2		0x1C

#define RGMII_IO_MACRO_DEBUG1		0x20

#define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28

#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	BIT(6)

#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	BIT(5)

struct ethqos_emac_por {

	unsigned int offset;

	unsigned int value;

};

struct qcom_ethqos {

	struct platform_device *pdev;

	void __iomem *rgmii_base;

	unsigned int rgmii_clk_rate;

	struct clk *rgmii_clk;

	unsigned int speed;

	const struct ethqos_emac_por *por;

	unsigned int num_por;

};

#define EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR 0x00000070

#define EMAC_HW_v2_3_2_RG 0x20030002

static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)

{

		      RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);

}

static const struct ethqos_emac_por emac_v2_3_0_por[] = {

	{ .offset = RGMII_IO_MACRO_CONFIG,	.value = 0x00C01343 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG,	.value = 0x2004642C },

	{ .offset = SDCC_HC_REG_DDR_CONFIG,	.value = 0x00000000 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG2,	.value = 0x00200000 },

	{ .offset = SDCC_USR_CTL,		.value = 0x00010800 },

	{ .offset = RGMII_IO_MACRO_CONFIG2,	.value = 0x00002060 },

};

static int ethqos_dll_configure(struct qcom_ethqos *ethqos)

{

	unsigned int val;

	int retry = 1000;

	/* Set CDR_EN */

	if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);

	else

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,

			      SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,

		      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);

	if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {

		rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);

		rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,

			      0, SDCC_HC_REG_DLL_CONFIG);

	}

	/* Wait for CK_OUT_EN clear */

	do {

		val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,

		      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);

	if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,

			      0, SDCC_HC_REG_DLL_CONFIG2);

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,

			      SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,

			      SDCC_HC_REG_DLL_CONFIG2);

	}

	return 0;

}

			      RGMII_IO_MACRO_CONFIG2);

		/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      69, SDCC_HC_REG_DDR_CONFIG);

		else

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      57, SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);

				      RGMII_CONFIG_LOOPBACK_EN,

				      RGMII_IO_MACRO_CONFIG);

		break;

	case SPEED_100:

			      BIT(6), RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      0, RGMII_IO_MACRO_CONFIG2);

		/* Write 0x5 to PRG_RCLK_DLY_CODE */

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);

				      RGMII_CONFIG_LOOPBACK_EN,

				      RGMII_IO_MACRO_CONFIG);

		break;

	case SPEED_10:

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

				      RGMII_IO_MACRO_CONFIG2);

		else

			rgmii_updatel(ethqos,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

				      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,

			      BIT(12) | GENMASK(9, 8),

			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      0, RGMII_IO_MACRO_CONFIG2);

		/* Write 0x5 to PRG_RCLK_DLY_CODE */

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);

				      RGMII_CONFIG_LOOPBACK_EN,

				      RGMII_IO_MACRO_CONFIG);

		break;

	default:

		dev_err(&ethqos->pdev->dev,

	if (ret)

		return ret;

	ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);

	if (!ethqos) {

		ret = -ENOMEM;

		goto err_mem;

	}

	ethqos->pdev = pdev;

	ethqos_init_reqgulators(ethqos);

	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);

	if (IS_ERR(plat_dat)) {

		dev_err(&pdev->dev, "dt configuration failed\n");

		return PTR_ERR(plat_dat);

	}

	ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);

	if (!ethqos) {

		ret = -ENOMEM;

		goto err_mem;

	}

	ethqos->pdev = pdev;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rgmii");

	ethqos->rgmii_base = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(ethqos->rgmii_base)) {

	if (ret)

		goto err_clk;

	ethqos->emac_ver = rgmii_readl(ethqos,

				       EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);

	rgmii_dump(ethqos);

	return ret;

	ret = stmmac_pltfr_remove(pdev);

	clk_disable_unprepare(ethqos->rgmii_clk);

	ethqos_disable_regulators(ethqos);

	return ret;

}

static const struct of_device_id qcom_ethqos_match[] = {

	{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_por},

	{ .compatible = "qcom,sdxprairie-ethqos", .data = &emac_v2_3_2_por},

	{ }

};

MODULE_DEVICE_TABLE(of, qcom_ethqos_match);

/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef	_DWMAC_QCOM_ETHQOS_H

#define	_DWMAC_QCOM_ETHQOS_H

#define DRV_NAME "qcom-ethqos"

#define ETHQOSDBG(fmt, args...) \

	pr_debug(DRV_NAME " %s:%d " fmt, __func__, ## args)

#define ETHQOSERR(fmt, args...) \

	pr_err(DRV_NAME " %s:%d " fmt, __func__, ## args)

#define ETHQOSINFO(fmt, args...) \

	pr_info(DRV_NAME " %s:%d " fmt, __func__, ## args)

#define RGMII_IO_MACRO_CONFIG		0x0

#define SDCC_HC_REG_DLL_CONFIG		0x4

#define SDCC_HC_REG_DDR_CONFIG		0xC

#define SDCC_HC_REG_DLL_CONFIG2		0x10

#define SDC4_STATUS			0x14

#define SDCC_USR_CTL			0x18

#define RGMII_IO_MACRO_CONFIG2		0x1C

struct ethqos_emac_por {

	unsigned int offset;

	unsigned int value;

};

static const struct ethqos_emac_por emac_v2_3_0_por[] = {

	{ .offset = RGMII_IO_MACRO_CONFIG,	.value = 0x00C01343 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG,	.value = 0x2004642C },

	{ .offset = SDCC_HC_REG_DDR_CONFIG,	.value = 0x00000000 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG2,	.value = 0x00200000 },

	{ .offset = SDCC_USR_CTL,		.value = 0x00010800 },

	{ .offset = RGMII_IO_MACRO_CONFIG2,	.value = 0x00002060 },

};

static const struct ethqos_emac_por emac_v2_3_2_por[] = {

	{ .offset = RGMII_IO_MACRO_CONFIG,	.value = 0x00C01343 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG,	.value = 0x2004642C },

	{ .offset = SDCC_HC_REG_DDR_CONFIG,	.value = 0x80040800 },

	{ .offset = SDCC_HC_REG_DLL_CONFIG2,	.value = 0x00200000 },

	{ .offset = SDCC_USR_CTL,		.value = 0x00010800 },

	{ .offset = RGMII_IO_MACRO_CONFIG2,	.value = 0x00002060 },

};

struct qcom_ethqos {

	struct platform_device *pdev;

	void __iomem *rgmii_base;

	unsigned int rgmii_clk_rate;

	struct clk *rgmii_clk;

	unsigned int speed;

	const struct ethqos_emac_por *por;

	unsigned int num_por;

	unsigned int emac_ver;

	struct regulator *gdsc_emac;

	struct regulator *reg_rgmii;

	struct regulator *reg_emac_phy;

	struct regulator *reg_rgmii_io_pads;

};

int ethqos_init_reqgulators(struct qcom_ethqos *ethqos);

void ethqos_disable_regulators(struct qcom_ethqos *ethqos);

#endif

/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/phy.h>

#include <linux/regulator/consumer.h>

#include "stmmac.h"

#include "dwmac-qcom-ethqos.h"

#define EMAC_GDSC_EMAC_NAME "gdsc_emac"

#define EMAC_VREG_RGMII_NAME "vreg_rgmii"

#define EMAC_VREG_EMAC_PHY_NAME "vreg_emac_phy"

#define EMAC_VREG_RGMII_IO_PADS_NAME "vreg_rgmii_io_pads"

int ethqos_init_reqgulators(struct qcom_ethqos *ethqos)

{

	int ret = 0;

	if (of_property_read_bool(ethqos->pdev->dev.of_node,

				  "gdsc_emac-supply")) {

		ethqos->gdsc_emac =

		devm_regulator_get(&ethqos->pdev->dev, EMAC_GDSC_EMAC_NAME);

		if (IS_ERR(ethqos->gdsc_emac)) {

			ETHQOSERR("Can not get <%s>\n", EMAC_GDSC_EMAC_NAME);

			return PTR_ERR(ethqos->gdsc_emac);

		}

		ret = regulator_enable(ethqos->gdsc_emac);

		if (ret) {

			ETHQOSERR("Can not enable <%s>\n", EMAC_GDSC_EMAC_NAME);

			goto reg_error;

		}

		ETHQOSDBG("Enabled <%s>\n", EMAC_GDSC_EMAC_NAME);

	}

	if (of_property_read_bool(ethqos->pdev->dev.of_node,

				  "vreg_rgmii-supply")) {

		ethqos->reg_rgmii =

		devm_regulator_get(&ethqos->pdev->dev, EMAC_VREG_RGMII_NAME);

		if (IS_ERR(ethqos->reg_rgmii)) {

			ETHQOSERR("Can not get <%s>\n", EMAC_VREG_RGMII_NAME);

			return PTR_ERR(ethqos->reg_rgmii);

		}

		ret = regulator_enable(ethqos->reg_rgmii);

		if (ret) {

			ETHQOSERR("Can not enable <%s>\n",

				  EMAC_VREG_RGMII_NAME);

			goto reg_error;

		}

		ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_RGMII_NAME);

	}

	if (of_property_read_bool(ethqos->pdev->dev.of_node,

				  "vreg_emac_phy-supply")) {

		ethqos->reg_emac_phy =

		devm_regulator_get(&ethqos->pdev->dev, EMAC_VREG_EMAC_PHY_NAME);

		if (IS_ERR(ethqos->reg_emac_phy)) {

			ETHQOSERR("Can not get <%s>\n",

				  EMAC_VREG_EMAC_PHY_NAME);

			return PTR_ERR(ethqos->reg_emac_phy);

		}

		ret = regulator_enable(ethqos->reg_emac_phy);

		if (ret) {

			ETHQOSERR("Can not enable <%s>\n",

				  EMAC_VREG_EMAC_PHY_NAME);

			goto reg_error;

		}

		ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_EMAC_PHY_NAME);

	}

	if (of_property_read_bool(ethqos->pdev->dev.of_node,

				  "vreg_rgmii_io_pads-supply")) {

		ethqos->reg_rgmii_io_pads = devm_regulator_get

		(&ethqos->pdev->dev, EMAC_VREG_RGMII_IO_PADS_NAME);

		if (IS_ERR(ethqos->reg_rgmii_io_pads)) {

			ETHQOSERR("Can not get <%s>\n",

				  EMAC_VREG_RGMII_IO_PADS_NAME);

			return PTR_ERR(ethqos->reg_rgmii_io_pads);

		}

		ret = regulator_enable(ethqos->reg_rgmii_io_pads);

		if (ret) {

			ETHQOSERR("Can not enable <%s>\n",

				  EMAC_VREG_RGMII_IO_PADS_NAME);

			goto reg_error;

		}

		ETHQOSDBG("Enabled <%s>\n", EMAC_VREG_RGMII_IO_PADS_NAME);

	}

	return ret;

reg_error:

	ETHQOSERR("%s failed\n", __func__);

	ethqos_disable_regulators(ethqos);

	return ret;

}

void ethqos_disable_regulators(struct qcom_ethqos *ethqos)

{

	if (ethqos->reg_rgmii) {

		regulator_disable(ethqos->reg_rgmii);

		devm_regulator_put(ethqos->reg_rgmii);

		ethqos->reg_rgmii = NULL;

	}

	if (ethqos->reg_emac_phy) {

		regulator_disable(ethqos->reg_emac_phy);

		devm_regulator_put(ethqos->reg_emac_phy);

		ethqos->reg_emac_phy = NULL;

	}

	if (ethqos->reg_rgmii_io_pads) {

		regulator_disable(ethqos->reg_rgmii_io_pads);

		devm_regulator_put(ethqos->reg_rgmii_io_pads);

		ethqos->reg_rgmii_io_pads = NULL;

	}

	if (ethqos->gdsc_emac) {

		regulator_disable(ethqos->gdsc_emac);

		devm_regulator_put(ethqos->gdsc_emac);

		ethqos->gdsc_emac = NULL;

	}

}