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Commit 849fb0de authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Inki Dae
Browse files

drm/exynos/hdmi: fix PLL for 27MHz settings 



Current settings for 27MHz and 27.027MHz do not work. Use the settings from
vendor code instead.

Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 10abdbc5

drivers/gpu/drm/exynos/exynos_hdmi.c

+6 −6
Original line number Diff line number Diff line
@@ -509,9 +509,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = { 
	{

		.pixel_clock = 27000000,

		.conf = {

			0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,

			0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,

			0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,

			0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,

			0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,

			0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,

			0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,

		},

	},
@@ -519,9 +519,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = { 
		.pixel_clock = 27027000,

		.conf = {

			0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,

			0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,

			0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,

			0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,

			0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,

			0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,

			0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,

		},

	},

	{