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Commit 83127d77 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "irqchip: gic-v3: support to get pending irqs and highprio irq"

parents e04cdd27 71acc6a5

arch/arm64/include/asm/arch_gicv3.h

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 


#include <asm/sysreg.h>



#define ICC_HPPIR1_EL1			sys_reg(3, 0, 12, 12, 2)



#ifndef __ASSEMBLY__



#include <linux/stringify.h>

drivers/irqchip/irq-gic-v3.c

+37 −0
Original line number Diff line number Diff line
@@ -146,6 +146,43 @@ static u64 __maybe_unused gic_read_iar(void) 
}

#endif



/*

 * gic_show_pending_irq - Shows the pending interrupts

 * Note: Interrupts should be disabled on the cpu from which

 * this is called to get accurate list of pending interrupts.

 */

void gic_show_pending_irqs(void)

{

	void __iomem *base;

	u32 pending, enabled;

	unsigned int j;



	base = gic_data.dist_base;

	for (j = 0; j * 32 < gic_data.irq_nr; j++) {

		enabled = readl_relaxed(base +

					GICD_ISENABLER + j * 4);

		pending = readl_relaxed(base +

					GICD_ISPENDR + j * 4);

		pr_err("Pending and enabled irqs[%d] %x %x\n", j,

				pending, enabled);

	}

}



/*

 * get_gic_highpri_irq - Returns next high priority interrupt on current CPU

 */

unsigned int get_gic_highpri_irq(void)

{

	unsigned long flags;

	unsigned int val = 0;



	local_irq_save(flags);

	val = read_gicreg(ICC_HPPIR1_EL1);

	local_irq_restore(flags);



	return val;

}



static void gic_enable_redist(bool enable)

{

	void __iomem *rbase;

include/linux/irqchip/arm-gic-v3.h

+2 −0
Original line number Diff line number Diff line
@@ -597,6 +597,8 @@ static inline bool gic_enable_sre(void) 
	return !!(val & ICC_SRE_EL1_SRE);

}



void gic_show_pending_irqs(void);

unsigned int get_gic_highpri_irq(void);

#endif



#endif