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Commit 82dfbd27 authored by Alan Douglas's avatar Alan Douglas Committed by Lorenzo Pieralisi
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dt-bindings: PCI: cadence: Add DT bindings for optional PHYs



Update DT documentation to include optional PHYs for cadence PCIe
host and endpoint controllers.

Signed-off-by: default avatarAlan Douglas <adouglas@cadence.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent dfb80534
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+5 −0
Original line number Diff line number Diff line
@@ -9,6 +9,9 @@ Required properties:

Optional properties:
- max-functions: Maximum number of functions that can be configured (default 1).
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
  than one in the list.  If only one PHY listed it must manage all lanes. 
- phy-names:  List of names to identify the PHY.

Example:

@@ -19,4 +22,6 @@ pcie@fc000000 {
	reg-names = "reg", "mem";
	cdns,max-outbound-regions = <16>;
	max-functions = /bits/ 8 <8>;
	phys = <&ep_phy0 &ep_phy1>;
	phy-names = "pcie-lane0","pcie-lane1";
};
+6 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ Optional properties:
  translations (default 32)
- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
- device-id: The PCI device ID (16 bits, default is design dependent)
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
  than one in the list.  If only one PHY listed it must manage all lanes. 
- phy-names:  List of names to identify the PHY.

Example:

@@ -57,4 +60,7 @@ pcie@fb000000 {
	interrupt-map-mask = <0x0 0x0 0x0  0x7>;

	msi-parent = <&its_pci>;

	phys = <&pcie_phy0>;
	phy-names = "pcie-phy";
};