Loading arch/arm/mach-omap2/io.c +10 −2 Original line number Original line Diff line number Diff line Loading @@ -734,7 +734,15 @@ int __init omap_clk_init(void) ti_clk_init_features(); ti_clk_init_features(); ret = of_prcm_init(); ret = of_prcm_init(); if (!ret) if (ret) return ret; of_clk_init(NULL); ti_dt_clk_init_retry_clks(); ti_dt_clockdomains_setup(); ret = omap_clk_soc_init(); ret = omap_clk_soc_init(); return ret; return ret; Loading arch/arm/mach-omap2/prm_common.c +0 −2 Original line number Original line Diff line number Diff line Loading @@ -525,8 +525,6 @@ int __init of_prcm_init(void) memmap_index++; memmap_index++; } } ti_dt_clockdomains_setup(); return 0; return 0; } } Loading drivers/clk/ti/clk-dra7-atl.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -203,6 +203,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) if (!IS_ERR(clk)) { if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(parent_names); return; return; } } cleanup: cleanup: Loading @@ -228,6 +229,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) cinfo->iobase = of_iomap(node, 0); cinfo->iobase = of_iomap(node, 0); cinfo->dev = &pdev->dev; cinfo->dev = &pdev->dev; pm_runtime_enable(cinfo->dev); pm_runtime_enable(cinfo->dev); pm_runtime_irq_safe(cinfo->dev); pm_runtime_get_sync(cinfo->dev); pm_runtime_get_sync(cinfo->dev); atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); Loading drivers/clk/ti/clk.c +43 −25 Original line number Original line Diff line number Diff line Loading @@ -25,8 +25,8 @@ #undef pr_fmt #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ #define pr_fmt(fmt) "%s: " fmt, __func__ static int ti_dt_clk_memmap_index; struct ti_clk_ll_ops *ti_clk_ll_ops; struct ti_clk_ll_ops *ti_clk_ll_ops; static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; /** /** * ti_dt_clocks_register - register DT alias clocks during boot * ti_dt_clocks_register - register DT alias clocks during boot Loading Loading @@ -108,9 +108,21 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) struct clk_omap_reg *reg; struct clk_omap_reg *reg; u32 val; u32 val; u32 tmp; u32 tmp; int i; reg = (struct clk_omap_reg *)&tmp; reg = (struct clk_omap_reg *)&tmp; reg->index = ti_dt_clk_memmap_index; for (i = 0; i < CLK_MAX_MEMMAPS; i++) { if (clocks_node_ptr[i] == node->parent) break; } if (i == CLK_MAX_MEMMAPS) { pr_err("clk-provider not found for %s!\n", node->name); return NULL; } reg->index = i; if (of_property_read_u32_index(node, "reg", index, &val)) { if (of_property_read_u32_index(node, "reg", index, &val)) { pr_err("%s must have reg[%d]!\n", node->name, index); pr_err("%s must have reg[%d]!\n", node->name, index); Loading @@ -127,20 +139,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) * @parent: master node * @parent: master node * @index: internal index for clk_reg_ops * @index: internal index for clk_reg_ops * * * Initializes a master clock IP block and its child clock nodes. * Initializes a master clock IP block. This basically sets up the * Regmap is provided for accessing the register space for the * mapping from clocks node to the memory map index. All the clocks * IP block and all the clocks under it. * are then initialized through the common of_clk_init call, and the * clocks will access their memory maps based on the node layout. */ */ void ti_dt_clk_init_provider(struct device_node *parent, int index) void ti_dt_clk_init_provider(struct device_node *parent, int index) { { const struct of_device_id *match; struct device_node *np; struct device_node *clocks; struct device_node *clocks; of_clk_init_cb_t clk_init_cb; struct clk_init_item *retry; struct clk_init_item *tmp; ti_dt_clk_memmap_index = index; /* get clocks for this parent */ /* get clocks for this parent */ clocks = of_get_child_by_name(parent, "clocks"); clocks = of_get_child_by_name(parent, "clocks"); Loading @@ -149,19 +155,31 @@ void ti_dt_clk_init_provider(struct device_node *parent, int index) return; return; } } for_each_child_of_node(clocks, np) { /* add clocks node info */ match = of_match_node(&__clk_of_table, np); clocks_node_ptr[index] = clocks; if (!match) continue; clk_init_cb = (of_clk_init_cb_t)match->data; pr_debug("%s: initializing: %s\n", __func__, np->name); clk_init_cb(np); } } /** * ti_dt_clk_init_retry_clks - init clocks from the retry list * * Initializes any clocks that have failed to initialize before, * reasons being missing parent node(s) during earlier init. This * typically happens only for DPLLs which need to have both of their * parent clocks ready during init. */ void ti_dt_clk_init_retry_clks(void) { struct clk_init_item *retry; struct clk_init_item *tmp; int retries = 5; while (!list_empty(&retry_list) && retries) { list_for_each_entry_safe(retry, tmp, &retry_list, link) { list_for_each_entry_safe(retry, tmp, &retry_list, link) { pr_debug("retry-init: %s\n", retry->node->name); pr_debug("retry-init: %s\n", retry->node->name); retry->func(retry->hw, retry->node); retry->func(retry->hw, retry->node); list_del(&retry->link); list_del(&retry->link); kfree(retry); kfree(retry); } } retries--; } } } drivers/clk/ti/clockdomain.c +5 −0 Original line number Original line Diff line number Diff line Loading @@ -36,6 +36,11 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) for (i = 0; i < num_clks; i++) { for (i = 0; i < num_clks; i++) { clk = of_clk_get(node, i); clk = of_clk_get(node, i); if (IS_ERR(clk)) { pr_err("%s: Failed get %s' clock nr %d (%ld)\n", __func__, node->full_name, i, PTR_ERR(clk)); continue; } if (__clk_get_flags(clk) & CLK_IS_BASIC) { if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); __clk_get_name(clk)); Loading Loading
arch/arm/mach-omap2/io.c +10 −2 Original line number Original line Diff line number Diff line Loading @@ -734,7 +734,15 @@ int __init omap_clk_init(void) ti_clk_init_features(); ti_clk_init_features(); ret = of_prcm_init(); ret = of_prcm_init(); if (!ret) if (ret) return ret; of_clk_init(NULL); ti_dt_clk_init_retry_clks(); ti_dt_clockdomains_setup(); ret = omap_clk_soc_init(); ret = omap_clk_soc_init(); return ret; return ret; Loading
arch/arm/mach-omap2/prm_common.c +0 −2 Original line number Original line Diff line number Diff line Loading @@ -525,8 +525,6 @@ int __init of_prcm_init(void) memmap_index++; memmap_index++; } } ti_dt_clockdomains_setup(); return 0; return 0; } } Loading
drivers/clk/ti/clk-dra7-atl.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -203,6 +203,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) if (!IS_ERR(clk)) { if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(parent_names); return; return; } } cleanup: cleanup: Loading @@ -228,6 +229,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) cinfo->iobase = of_iomap(node, 0); cinfo->iobase = of_iomap(node, 0); cinfo->dev = &pdev->dev; cinfo->dev = &pdev->dev; pm_runtime_enable(cinfo->dev); pm_runtime_enable(cinfo->dev); pm_runtime_irq_safe(cinfo->dev); pm_runtime_get_sync(cinfo->dev); pm_runtime_get_sync(cinfo->dev); atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); Loading
drivers/clk/ti/clk.c +43 −25 Original line number Original line Diff line number Diff line Loading @@ -25,8 +25,8 @@ #undef pr_fmt #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ #define pr_fmt(fmt) "%s: " fmt, __func__ static int ti_dt_clk_memmap_index; struct ti_clk_ll_ops *ti_clk_ll_ops; struct ti_clk_ll_ops *ti_clk_ll_ops; static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; /** /** * ti_dt_clocks_register - register DT alias clocks during boot * ti_dt_clocks_register - register DT alias clocks during boot Loading Loading @@ -108,9 +108,21 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) struct clk_omap_reg *reg; struct clk_omap_reg *reg; u32 val; u32 val; u32 tmp; u32 tmp; int i; reg = (struct clk_omap_reg *)&tmp; reg = (struct clk_omap_reg *)&tmp; reg->index = ti_dt_clk_memmap_index; for (i = 0; i < CLK_MAX_MEMMAPS; i++) { if (clocks_node_ptr[i] == node->parent) break; } if (i == CLK_MAX_MEMMAPS) { pr_err("clk-provider not found for %s!\n", node->name); return NULL; } reg->index = i; if (of_property_read_u32_index(node, "reg", index, &val)) { if (of_property_read_u32_index(node, "reg", index, &val)) { pr_err("%s must have reg[%d]!\n", node->name, index); pr_err("%s must have reg[%d]!\n", node->name, index); Loading @@ -127,20 +139,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) * @parent: master node * @parent: master node * @index: internal index for clk_reg_ops * @index: internal index for clk_reg_ops * * * Initializes a master clock IP block and its child clock nodes. * Initializes a master clock IP block. This basically sets up the * Regmap is provided for accessing the register space for the * mapping from clocks node to the memory map index. All the clocks * IP block and all the clocks under it. * are then initialized through the common of_clk_init call, and the * clocks will access their memory maps based on the node layout. */ */ void ti_dt_clk_init_provider(struct device_node *parent, int index) void ti_dt_clk_init_provider(struct device_node *parent, int index) { { const struct of_device_id *match; struct device_node *np; struct device_node *clocks; struct device_node *clocks; of_clk_init_cb_t clk_init_cb; struct clk_init_item *retry; struct clk_init_item *tmp; ti_dt_clk_memmap_index = index; /* get clocks for this parent */ /* get clocks for this parent */ clocks = of_get_child_by_name(parent, "clocks"); clocks = of_get_child_by_name(parent, "clocks"); Loading @@ -149,19 +155,31 @@ void ti_dt_clk_init_provider(struct device_node *parent, int index) return; return; } } for_each_child_of_node(clocks, np) { /* add clocks node info */ match = of_match_node(&__clk_of_table, np); clocks_node_ptr[index] = clocks; if (!match) continue; clk_init_cb = (of_clk_init_cb_t)match->data; pr_debug("%s: initializing: %s\n", __func__, np->name); clk_init_cb(np); } } /** * ti_dt_clk_init_retry_clks - init clocks from the retry list * * Initializes any clocks that have failed to initialize before, * reasons being missing parent node(s) during earlier init. This * typically happens only for DPLLs which need to have both of their * parent clocks ready during init. */ void ti_dt_clk_init_retry_clks(void) { struct clk_init_item *retry; struct clk_init_item *tmp; int retries = 5; while (!list_empty(&retry_list) && retries) { list_for_each_entry_safe(retry, tmp, &retry_list, link) { list_for_each_entry_safe(retry, tmp, &retry_list, link) { pr_debug("retry-init: %s\n", retry->node->name); pr_debug("retry-init: %s\n", retry->node->name); retry->func(retry->hw, retry->node); retry->func(retry->hw, retry->node); list_del(&retry->link); list_del(&retry->link); kfree(retry); kfree(retry); } } retries--; } } }
drivers/clk/ti/clockdomain.c +5 −0 Original line number Original line Diff line number Diff line Loading @@ -36,6 +36,11 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) for (i = 0; i < num_clks; i++) { for (i = 0; i < num_clks; i++) { clk = of_clk_get(node, i); clk = of_clk_get(node, i); if (IS_ERR(clk)) { pr_err("%s: Failed get %s' clock nr %d (%ld)\n", __func__, node->full_name, i, PTR_ERR(clk)); continue; } if (__clk_get_flags(clk) & CLK_IS_BASIC) { if (__clk_get_flags(clk) & CLK_IS_BASIC) { pr_warn("can't setup clkdm for basic clk %s\n", pr_warn("can't setup clkdm for basic clk %s\n", __clk_get_name(clk)); __clk_get_name(clk)); Loading