Loading drivers/gpu/msm/adreno_a6xx_gmu.c +0 −4 Original line number Diff line number Diff line Loading @@ -48,10 +48,6 @@ static const unsigned int a6xx_gmu_registers[] = { 0x1F957, 0x1F958, 0x1F95D, 0x1F95D, 0x1F962, 0x1F962, 0x1F964, 0x1F965, 0x1F980, 0x1F986, 0x1F990, 0x1F99E, 0x1F9C0, 0x1F9C0, 0x1F9C5, 0x1F9CC, 0x1F9E0, 0x1F9E2, 0x1F9F0, 0x1F9F0, 0x1FA00, 0x1FA01, /* GPU RSCC */ 0x2348C, 0x2348C, 0x23501, 0x23502, 0x23740, 0x23742, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, /* GMU AO */ 0x23B00, 0x23B16, 0x23C00, 0x23C00, /* GPU CC */ Loading drivers/gpu/msm/adreno_a6xx_snapshot.c +27 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,24 @@ static const unsigned int a6xx_pc_vs_cluster[] = { 0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9B00, 0x9B07, }; static const unsigned int a630_rscc_snapshot_registers[] = { 0x23400, 0x23434, 0x23436, 0x23436, 0x23480, 0x23484, 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, }; static const unsigned int a6xx_rscc_snapshot_registers[] = { 0x23400, 0x23434, 0x23436, 0x23436, 0x23440, 0x23440, 0x23480, 0x23484, 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, }; static const struct sel_reg { unsigned int host_reg; unsigned int cd_reg; Loading Loading @@ -1542,6 +1560,15 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, snapshot, a6xx_snapshot_registers, &a6xx_reg_list[i]); } if (adreno_is_a615(adreno_dev) || adreno_is_a630(adreno_dev)) adreno_snapshot_registers(device, snapshot, a630_rscc_snapshot_registers, ARRAY_SIZE(a630_rscc_snapshot_registers) / 2); else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) adreno_snapshot_registers(device, snapshot, a6xx_rscc_snapshot_registers, ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2); /* CP_SQE indexed registers */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33); Loading Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +0 −4 Original line number Diff line number Diff line Loading @@ -48,10 +48,6 @@ static const unsigned int a6xx_gmu_registers[] = { 0x1F957, 0x1F958, 0x1F95D, 0x1F95D, 0x1F962, 0x1F962, 0x1F964, 0x1F965, 0x1F980, 0x1F986, 0x1F990, 0x1F99E, 0x1F9C0, 0x1F9C0, 0x1F9C5, 0x1F9CC, 0x1F9E0, 0x1F9E2, 0x1F9F0, 0x1F9F0, 0x1FA00, 0x1FA01, /* GPU RSCC */ 0x2348C, 0x2348C, 0x23501, 0x23502, 0x23740, 0x23742, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, /* GMU AO */ 0x23B00, 0x23B16, 0x23C00, 0x23C00, /* GPU CC */ Loading
drivers/gpu/msm/adreno_a6xx_snapshot.c +27 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,24 @@ static const unsigned int a6xx_pc_vs_cluster[] = { 0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9B00, 0x9B07, }; static const unsigned int a630_rscc_snapshot_registers[] = { 0x23400, 0x23434, 0x23436, 0x23436, 0x23480, 0x23484, 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, }; static const unsigned int a6xx_rscc_snapshot_registers[] = { 0x23400, 0x23434, 0x23436, 0x23436, 0x23440, 0x23440, 0x23480, 0x23484, 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, }; static const struct sel_reg { unsigned int host_reg; unsigned int cd_reg; Loading Loading @@ -1542,6 +1560,15 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, snapshot, a6xx_snapshot_registers, &a6xx_reg_list[i]); } if (adreno_is_a615(adreno_dev) || adreno_is_a630(adreno_dev)) adreno_snapshot_registers(device, snapshot, a630_rscc_snapshot_registers, ARRAY_SIZE(a630_rscc_snapshot_registers) / 2); else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) adreno_snapshot_registers(device, snapshot, a6xx_rscc_snapshot_registers, ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2); /* CP_SQE indexed registers */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33); Loading