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Commit 80c517b0 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon
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arm64: add helper functions to read I-cache attributes 



This adds helper functions and #defines to <asm/cachetype.h> to read the
line size and the number of sets from the level 1 instruction cache.

Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 2ce7598c

arch/arm64/include/asm/cachetype.h

+20 −0
Original line number Original line Diff line number Diff line
@@ -39,6 +39,26 @@ 




extern unsigned long __icache_flags;

extern unsigned long __icache_flags;





#define CCSIDR_EL1_LINESIZE_MASK	0x7

#define CCSIDR_EL1_LINESIZE(x)		((x) & CCSIDR_EL1_LINESIZE_MASK)



#define CCSIDR_EL1_NUMSETS_SHIFT	13

#define CCSIDR_EL1_NUMSETS_MASK		(0x7fff << CCSIDR_EL1_NUMSETS_SHIFT)

#define CCSIDR_EL1_NUMSETS(x) \

	(((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT)



extern u64 __attribute_const__ icache_get_ccsidr(void);



static inline int icache_get_linesize(void)

{

	return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr());

}



static inline int icache_get_numsets(void)

{

	return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr());

}



/*

/*

 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is

 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is

 * permitted in the I-cache.

 * permitted in the I-cache.

arch/arm64/kernel/cpuinfo.c

+14 −0
Original line number Original line Diff line number Diff line
@@ -20,8 +20,10 @@ 
#include <asm/cputype.h>

#include <asm/cputype.h>





#include <linux/bitops.h>

#include <linux/bitops.h>

#include <linux/bug.h>

#include <linux/init.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/kernel.h>

#include <linux/preempt.h>

#include <linux/printk.h>

#include <linux/printk.h>

#include <linux/smp.h>

#include <linux/smp.h>
@@ -190,3 +192,15 @@ void __init cpuinfo_store_boot_cpu(void) 




	boot_cpu_data = *info;

	boot_cpu_data = *info;

}

}



u64 __attribute_const__ icache_get_ccsidr(void)

{

	u64 ccsidr;



	WARN_ON(preemptible());



	/* Select L1 I-cache and read its size ID register */

	asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"

	    : "=r"(ccsidr) : "r"(1L));

	return ccsidr;

}