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Commit 8005c6ae authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "wil6210: increase RX rings and RX buff array size"

parents 9378287d 4c7604b7
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+8 −3
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static const struct kernel_param_ops mtu_max_ops = {
module_param_cb(mtu_max, &mtu_max_ops, &mtu_max, 0444);
MODULE_PARM_DESC(mtu_max, " Max MTU value.");

static uint rx_ring_order	 = WIL_RX_RING_SIZE_ORDER_DEFAULT;
static uint rx_ring_order;
static uint tx_ring_order = WIL_TX_RING_SIZE_ORDER_DEFAULT;
static uint bcast_ring_order = WIL_BCAST_RING_SIZE_ORDER_DEFAULT;

@@ -1718,6 +1718,11 @@ int __wil_up(struct wil6210_priv *wil)
		return rc;

	/* Rx RING. After MAC and beacon */
	if (rx_ring_order == 0)
		rx_ring_order = wil->hw_version < HW_VER_TALYN_MB ?
			WIL_RX_RING_SIZE_ORDER_DEFAULT :
			WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT;

	rc = wil->txrx_ops.rx_init(wil, 1 << rx_ring_order);
	if (rc)
		return rc;
+2 −2
Original line number Diff line number Diff line
@@ -358,8 +358,8 @@ static int wil_init_rx_sring(struct wil6210_priv *wil,
	struct wil_status_ring *sring = &wil->srings[ring_id];
	int rc;

	wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", sring->size,
		     ring_id);
	wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n",
		     status_ring_size, ring_id);

	memset(&sring->rx_data, 0, sizeof(sring->rx_data));

+2 −2
Original line number Diff line number Diff line
@@ -23,9 +23,9 @@
#define WIL_SRING_SIZE_ORDER_MIN	(WIL_RING_SIZE_ORDER_MIN)
#define WIL_SRING_SIZE_ORDER_MAX	(WIL_RING_SIZE_ORDER_MAX)
/* RX sring order should be bigger than RX ring order */
#define WIL_RX_SRING_SIZE_ORDER_DEFAULT	(11)
#define WIL_RX_SRING_SIZE_ORDER_DEFAULT	(12)
#define WIL_TX_SRING_SIZE_ORDER_DEFAULT	(12)
#define WIL_RX_BUFF_ARR_SIZE_DEFAULT (1536)
#define WIL_RX_BUFF_ARR_SIZE_DEFAULT (2600)

#define WIL_DEFAULT_RX_STATUS_RING_ID 0
#define WIL_RX_DESC_RING_ID 0
+1 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)

#define WIL_TX_Q_LEN_DEFAULT		(4000)
#define WIL_RX_RING_SIZE_ORDER_DEFAULT	(10)
#define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT	(11)
#define WIL_TX_RING_SIZE_ORDER_DEFAULT	(12)
#define WIL_BCAST_RING_SIZE_ORDER_DEFAULT	(7)
#define WIL_BCAST_MCS0_LIMIT		(1024) /* limit for MCS0 frame size */