Merge "ARM: dts: msm: Add dtsi support for v150_110 camera" into dev/msm-4.14-camx

* Qualcomm Technologies, Inc. MSM camera PPI

=======================

Required Node Structure

=======================

The camera PPI node must be described in First level of device nodes. The

first level describe the overall PPI node structure.

======================================

First Level Node - PPI device

======================================

- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,ppi-v1.0",

        "qcom,ppi-v1.1", "qcom,ppi-v1.2",

        "qcom,ppi-v2.0", "qcom,ppi".

- cell-index: ppi hardware core index

  Usage: required

  Value type: <u32>

  Definition: Should specify the Hardware index id.

- reg

  Usage: required

  Value type: <u32>

  Definition: offset and length of the register set

        for the device for the ppi operating in

        compatible mode.

- reg-names

  Usage: required

  Value type: <string>

  Definition: Should specify relevant names to each

        reg property defined.

- reg-cam-base

  Usage: required

  Value type: <string>

  Definition: offset of PPI in  camera hw block

- interrupts

  Usage: required

  Value type: <u32>

  Definition: Interrupt associated with PPI HW.

- interrupt-names

  Usage: required

  Value type: <string>

  Definition: Name of the interrupt.

- clock-names

  Usage: required

  Value type: <string>

  Definition: List of clock names required for PPI HW.

- clock-rates

  Usage: required

  Value type: <u32>

  Definition: List of clock rates in Hz for PPI HW.

- clock-cntl-level

  Usage: required

  Value type: <string>

  Definition: All different clock level node can support.

- clocks

  Usage: required

  Value type: <phandle>

  Definition: all clock phandle and source clocks.

- regulator-names

  Usage: required

  Value type: <string>

  Definition: name of the voltage regulators required for the device.

- gdscr-supply

  Usage: required

  Value type: <phandle>

  Definition: should contain gdsr regulator used for PPI clocks.

Example:

     qcom,ppi0@ace0000 {

     cell-index = <0>;

     compatible = "qcom,ppi170";

     reg-names = "ppi";

     reg = <0xace0000 0x200>;

     reg-cam-base = <0xe0000>;

     interrupt-names = "ppi";

     interrupts = <0 202 0>;

     regulator-names = "gdscr", "refgen";

     gdscr-supply = <&titan_top_gdsc>;

     clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

              <&clock_camcc CAM_CC_PPI0_CLK>,

              <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

              <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

     clock-names = "cphy_rx_clk_src", "ppi0_clk"

     clock-rates = <400000000 0 300000000 0>;

     clock-cntl-level = "turbo";

     status = "ok";

};