staging: ccree: simplify ioread/iowrite (7f5ce9dd) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/staging/ccree/cc_hal.h

deleted100644 → 0

+0 −33

Original line number	Original line	Diff line number	Diff line
	/*
	* Copyright (C) 2012-2017 ARM Limited or its affiliates.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	*/

	/* pseudo cc_hal.h for cc7x_perf_test_driver (to be able to include code from
	* CC drivers).
	*/

	#ifndef __CC_HAL_H__
	#define __CC_HAL_H__

	#include <linux/io.h>

	#define READ_REGISTER(_addr) ioread32((_addr))
	#define WRITE_REGISTER(_addr, _data) iowrite32((_data), (_addr))

	#define CC_HAL_WRITE_REGISTER(offset, val) \
	WRITE_REGISTER(cc_base + (offset), val)
	#define CC_HAL_READ_REGISTER(offset) READ_REGISTER(cc_base + (offset))

	#endif

drivers/staging/ccree/cc_regs.h

deleted100644 → 0

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	/*
	* Copyright (C) 2012-2017 ARM Limited or its affiliates.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	*/

	/*!
	* @file
	* @brief This file contains macro definitions for accessing ARM TrustZone
	* CryptoCell register space.
	*/

	#ifndef _CC_REGS_H_
	#define _CC_REGS_H_

	#include <linux/bitfield.h>

	#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
	DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
	DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)

	/* Register name mangling macro */
	#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET

	#endif /_CC_REGS_H_/

drivers/staging/ccree/dx_reg_base_host.h

deleted100644 → 0

+0 −25

Original line number	Original line	Diff line number	Diff line
	/*
	* Copyright (C) 2012-2017 ARM Limited or its affiliates.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	*/

	#ifndef __DX_REG_BASE_HOST_H__
	#define __DX_REG_BASE_HOST_H__

	#define DX_BASE_CC 0x80000000
	#define DX_BASE_HOST_RGF 0x0UL
	#define DX_BASE_CRY_KERNEL 0x0UL
	#define DX_BASE_ROM 0x40000000

	#endif /__DX_REG_BASE_HOST_H__/

drivers/staging/ccree/ssi_driver.c

+21 −26

Original line number	Original line	Diff line number	Diff line
	@@ -91,7 +91,6 @@ void dump_byte_array(const char name, const u8 buf, size_t len)
	static irqreturn_t cc_isr(int irq, void *dev_id)		static irqreturn_t cc_isr(int irq, void *dev_id)
	{		{
	struct ssi_drvdata drvdata = (struct ssi_drvdata )dev_id;		struct ssi_drvdata drvdata = (struct ssi_drvdata )dev_id;
	void __iomem *cc_base = drvdata->cc_base;
	struct device *dev = drvdata_to_dev(drvdata);		struct device *dev = drvdata_to_dev(drvdata);
	u32 irr;		u32 irr;
	u32 imr;		u32 imr;
	@@ -99,22 +98,22 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
	/* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */		/* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */

	/* read the interrupt status */		/* read the interrupt status */
	irr = CC_HAL_READ_REGISTER(CC_REG(HOST_IRR));		irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
	dev_dbg(dev, "Got IRR=0x%08X\n", irr);		dev_dbg(dev, "Got IRR=0x%08X\n", irr);
	if (unlikely(irr == 0)) { /* Probably shared interrupt line */		if (unlikely(irr == 0)) { /* Probably shared interrupt line */
	dev_err(dev, "Got interrupt with empty IRR\n");		dev_err(dev, "Got interrupt with empty IRR\n");
	return IRQ_NONE;		return IRQ_NONE;
	}		}
	imr = CC_HAL_READ_REGISTER(CC_REG(HOST_IMR));		imr = cc_ioread(drvdata, CC_REG(HOST_IMR));

	/* clear interrupt - must be before processing events */		/* clear interrupt - must be before processing events */
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), irr);		cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);

	drvdata->irq = irr;		drvdata->irq = irr;
	/* Completion interrupt - most probable */		/* Completion interrupt - most probable */
	if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) {		if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) {
	/* Mask AXI completion interrupt - will be unmasked in Deferred service handler */		/* Mask AXI completion interrupt - will be unmasked in Deferred service handler */
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), imr \| SSI_COMP_IRQ_MASK);		cc_iowrite(drvdata, CC_REG(HOST_IMR), imr \| SSI_COMP_IRQ_MASK);
	irr &= ~SSI_COMP_IRQ_MASK;		irr &= ~SSI_COMP_IRQ_MASK;
	complete_request(drvdata);		complete_request(drvdata);
	}		}
	@@ -122,7 +121,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
	/* TEE FIPS interrupt */		/* TEE FIPS interrupt */
	if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) {		if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) {
	/* Mask interrupt - will be unmasked in Deferred service handler */		/* Mask interrupt - will be unmasked in Deferred service handler */
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), imr \| SSI_GPR0_IRQ_MASK);		cc_iowrite(drvdata, CC_REG(HOST_IMR), imr \| SSI_GPR0_IRQ_MASK);
	irr &= ~SSI_GPR0_IRQ_MASK;		irr &= ~SSI_GPR0_IRQ_MASK;
	fips_handler(drvdata);		fips_handler(drvdata);
	}		}
	@@ -132,7 +131,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
	u32 axi_err;		u32 axi_err;

	/* Read the AXI error ID */		/* Read the AXI error ID */
	axi_err = CC_HAL_READ_REGISTER(CC_REG(AXIM_MON_ERR));		axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
	dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",		dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",
	axi_err);		axi_err);

	@@ -151,47 +150,44 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
	int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)		int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
	{		{
	unsigned int val, cache_params;		unsigned int val, cache_params;
	void __iomem *cc_base = drvdata->cc_base;
	struct device *dev = drvdata_to_dev(drvdata);		struct device *dev = drvdata_to_dev(drvdata);

	/* Unmask all AXI interrupt sources AXI_CFG1 register */		/* Unmask all AXI interrupt sources AXI_CFG1 register */
	val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CFG));		val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
	CC_HAL_WRITE_REGISTER(CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK);		cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK);
	dev_dbg(dev, "AXIM_CFG=0x%08X\n",		dev_dbg(dev, "AXIM_CFG=0x%08X\n",
	CC_HAL_READ_REGISTER(CC_REG(AXIM_CFG)));		cc_ioread(drvdata, CC_REG(AXIM_CFG)));

	/* Clear all pending interrupts */		/* Clear all pending interrupts */
	val = CC_HAL_READ_REGISTER(CC_REG(HOST_IRR));		val = cc_ioread(drvdata, CC_REG(HOST_IRR));
	dev_dbg(dev, "IRR=0x%08X\n", val);		dev_dbg(dev, "IRR=0x%08X\n", val);
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), val);		cc_iowrite(drvdata, CC_REG(HOST_ICR), val);

	/* Unmask relevant interrupt cause */		/* Unmask relevant interrupt cause */
	val = (unsigned int)(~(SSI_COMP_IRQ_MASK \| SSI_AXI_ERR_IRQ_MASK \|		val = (unsigned int)(~(SSI_COMP_IRQ_MASK \| SSI_AXI_ERR_IRQ_MASK \|
	SSI_GPR0_IRQ_MASK));		SSI_GPR0_IRQ_MASK));
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), val);		cc_iowrite(drvdata, CC_REG(HOST_IMR), val);

	#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET		#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET
	#ifdef DX_IRQ_DELAY		#ifdef DX_IRQ_DELAY
	/* Set CC IRQ delay */		/* Set CC IRQ delay */
	CC_HAL_WRITE_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL),		cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), DX_IRQ_DELAY);
	DX_IRQ_DELAY);
	#endif		#endif
	if (CC_HAL_READ_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) {		if (cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) {
	dev_dbg(dev, "irq_delay=%d CC cycles\n",		dev_dbg(dev, "irq_delay=%d CC cycles\n",
	CC_HAL_READ_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL)));		cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)));
	}		}
	#endif		#endif

	cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);		cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);

	val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CACHE_PARAMS));		val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));

	if (is_probe)		if (is_probe)
	dev_info(dev, "Cache params previous: 0x%08X\n", val);		dev_info(dev, "Cache params previous: 0x%08X\n", val);

	CC_HAL_WRITE_REGISTER(CC_REG(AXIM_CACHE_PARAMS),		cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
	cache_params);		val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
	val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CACHE_PARAMS));

	if (is_probe)		if (is_probe)
	dev_info(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",		dev_info(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",
	@@ -280,7 +276,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
	}		}

	/* Verify correct mapping */		/* Verify correct mapping */
	signature_val = CC_HAL_READ_REGISTER(CC_REG(HOST_SIGNATURE));		signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
	if (signature_val != DX_DEV_SIGNATURE) {		if (signature_val != DX_DEV_SIGNATURE) {
	dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",		dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
	signature_val, (u32)DX_DEV_SIGNATURE);		signature_val, (u32)DX_DEV_SIGNATURE);
	@@ -292,7 +288,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
	/* Display HW versions */		/* Display HW versions */
	dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",		dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
	SSI_DEV_NAME_STR,		SSI_DEV_NAME_STR,
	CC_HAL_READ_REGISTER(CC_REG(HOST_VERSION)),		cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),
	DRV_MODULE_VERSION);		DRV_MODULE_VERSION);

	rc = init_cc_regs(new_drvdata, true);		rc = init_cc_regs(new_drvdata, true);
	@@ -410,8 +406,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
	void fini_cc_regs(struct ssi_drvdata *drvdata)		void fini_cc_regs(struct ssi_drvdata *drvdata)
	{		{
	/* Mask all interrupts */		/* Mask all interrupts */
	WRITE_REGISTER(drvdata->cc_base +		cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);
	CC_REG(HOST_IMR), 0xFFFFFFFF);
	}		}

	static void cleanup_cc_resources(struct platform_device *plat_dev)		static void cleanup_cc_resources(struct platform_device *plat_dev)

drivers/staging/ccree/ssi_driver.h

+17 −3

Original line number	Original line	Diff line number	Diff line
	@@ -40,11 +40,8 @@
	#include <linux/platform_device.h>		#include <linux/platform_device.h>

	/* Registers definitions from shared/hw/ree_include */		/* Registers definitions from shared/hw/ree_include */
	#include "dx_reg_base_host.h"
	#include "dx_host.h"		#include "dx_host.h"
	#include "cc_regs.h"
	#include "dx_reg_common.h"		#include "dx_reg_common.h"
	#include "cc_hal.h"
	#define CC_SUPPORT_SHA DX_DEV_SHA_MAX		#define CC_SUPPORT_SHA DX_DEV_SHA_MAX
	#include "cc_crypto_ctx.h"		#include "cc_crypto_ctx.h"
	#include "ssi_sysfs.h"		#include "ssi_sysfs.h"
	@@ -73,6 +70,13 @@

	#define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)		#define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)

			#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
			DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
			DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)

			/* Register name mangling macro */
			#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET

	/* TEE FIPS status interrupt */		/* TEE FIPS status interrupt */
	#define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT)		#define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT)

	@@ -188,5 +192,15 @@ void fini_cc_regs(struct ssi_drvdata *drvdata);
	int cc_clk_on(struct ssi_drvdata *drvdata);		int cc_clk_on(struct ssi_drvdata *drvdata);
	void cc_clk_off(struct ssi_drvdata *drvdata);		void cc_clk_off(struct ssi_drvdata *drvdata);

			static inline void cc_iowrite(struct ssi_drvdata *drvdata, u32 reg, u32 val)
			{
			iowrite32(val, (drvdata->cc_base + reg));
			}

			static inline u32 cc_ioread(struct ssi_drvdata *drvdata, u32 reg)
			{
			return ioread32(drvdata->cc_base + reg);
			}

	#endif /__SSI_DRIVER_H__/		#endif /__SSI_DRIVER_H__/