Commit 7f2ea384 authored Mar 23, 2016 by Maxime Ripard

dt-bindings: clk: sun5i: add DRAM gates compatible



The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent f4b9ef65

Documentation/devicetree/bindings/clock/sunxi.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -64,6 +64,7 @@ Required properties:
		"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
		"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
		"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
		"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
		"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
		"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
		"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80