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Commit 7f02ab3c authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6: (25 commits)
  serial: Tidy REMOTE_DEBUG
  serial: isicomm: handle running out of slots
  serial: bfin_sport_uart: Use resource size to fix off-by-one error
  tty: fix obsolete comment on tty_insert_flip_string_fixed_flag
  serial: Add driver for the Altera UART
  serial: Add driver for the Altera JTAG UART
  serial: timbuart: make sure last byte is sent when port is closed
  serial: two branches the same in timbuart_set_mctrl()
  serial: uartlite: move from byte accesses to word accesses
  tty: n_gsm: depends on NET
  tty: n_gsm line discipline
  serial: TTY: new ldiscs for staging
  serial: bfin_sport_uart: drop redundant cpu depends
  serial: bfin_sport_uart: drop the experimental markings
  serial: bfin_sport_uart: pull in bfin_sport.h for SPORT defines
  serial: bfin_sport_uart: only enable SPORT TX if data is to be sent
  serial: bfin_sport_uart: drop useless status masks
  serial: bfin_sport_uart: zero sport_uart_port if allocated dynamically
  serial: bfin_sport_uart: protect changes to uart_port
  serial: bfin_sport_uart: add support for CTS/RTS via GPIOs
  ...
parents d6fb1db0 0dbb5671
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+9 −1
Original line number Original line Diff line number Diff line
@@ -276,11 +276,19 @@ config N_HDLC
	  Allows synchronous HDLC communications with tty device drivers that
	  Allows synchronous HDLC communications with tty device drivers that
	  support synchronous HDLC such as the Microgate SyncLink adapter.
	  support synchronous HDLC such as the Microgate SyncLink adapter.


	  This driver can only be built as a module ( = code which can be
	  This driver can be built as a module ( = code which can be
	  inserted in and removed from the running kernel whenever you want).
	  inserted in and removed from the running kernel whenever you want).
	  The module will be called n_hdlc. If you want to do that, say M
	  The module will be called n_hdlc. If you want to do that, say M
	  here.
	  here.


config N_GSM
	tristate "GSM MUX line discipline support (EXPERIMENTAL)"
	depends on EXPERIMENTAL
	depends on NET
	help
	  This line discipline provides support for the GSM MUX protocol and
	  presents the mux as a set of 61 individual tty devices.

config RISCOM8
config RISCOM8
	tristate "SDL RISCom/8 card support"
	tristate "SDL RISCom/8 card support"
	depends on SERIAL_NONSTANDARD
	depends on SERIAL_NONSTANDARD
+1 −0
Original line number Original line Diff line number Diff line
@@ -40,6 +40,7 @@ obj-$(CONFIG_SYNCLINK) += synclink.o
obj-$(CONFIG_SYNCLINKMP)	+= synclinkmp.o
obj-$(CONFIG_SYNCLINKMP)	+= synclinkmp.o
obj-$(CONFIG_SYNCLINK_GT)	+= synclink_gt.o
obj-$(CONFIG_SYNCLINK_GT)	+= synclink_gt.o
obj-$(CONFIG_N_HDLC)		+= n_hdlc.o
obj-$(CONFIG_N_HDLC)		+= n_hdlc.o
obj-$(CONFIG_N_GSM)		+= n_gsm.o
obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
obj-$(CONFIG_SX)		+= sx.o generic_serial.o
obj-$(CONFIG_SX)		+= sx.o generic_serial.o
obj-$(CONFIG_RIO)		+= rio/ generic_serial.o
obj-$(CONFIG_RIO)		+= rio/ generic_serial.o
+7 −1
Original line number Original line Diff line number Diff line
@@ -1573,11 +1573,16 @@ static int __devinit isicom_probe(struct pci_dev *pdev,
	dev_info(&pdev->dev, "ISI PCI Card(Device ID 0x%x)\n", ent->device);
	dev_info(&pdev->dev, "ISI PCI Card(Device ID 0x%x)\n", ent->device);


	/* allot the first empty slot in the array */
	/* allot the first empty slot in the array */
	for (index = 0; index < BOARD_COUNT; index++)
	for (index = 0; index < BOARD_COUNT; index++) {
		if (isi_card[index].base == 0) {
		if (isi_card[index].base == 0) {
			board = &isi_card[index];
			board = &isi_card[index];
			break;
			break;
		}
		}
	}
	if (index == BOARD_COUNT) {
		retval = -ENODEV;
		goto err_disable;
	}


	board->index = index;
	board->index = index;
	board->base = pci_resource_start(pdev, 3);
	board->base = pci_resource_start(pdev, 3);
@@ -1624,6 +1629,7 @@ static int __devinit isicom_probe(struct pci_dev *pdev,
errdec:
errdec:
	board->base = 0;
	board->base = 0;
	card_count--;
	card_count--;
err_disable:
	pci_disable_device(pdev);
	pci_disable_device(pdev);
err:
err:
	return retval;
	return retval;

drivers/char/n_gsm.c

0 → 100644
+2763 −0

File added.

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+1 −222
Original line number Original line Diff line number Diff line
@@ -176,23 +176,6 @@ static void config_setup(struct cyclades_port *);
static void show_status(int);
static void show_status(int);
#endif
#endif


#ifdef CONFIG_REMOTE_DEBUG
static void debug_setup(void);
void queueDebugChar(int c);
int getDebugChar(void);

#define DEBUG_PORT	1
#define DEBUG_LEN	256

typedef struct {
	int in;
	int out;
	unsigned char buf[DEBUG_LEN];
} debugq;

debugq debugiq;
#endif

/*
/*
 * I have my own version of udelay(), as it is needed when initialising
 * I have my own version of udelay(), as it is needed when initialising
 * the chip, before the delay loop has been calibrated.  Should probably
 * the chip, before the delay loop has been calibrated.  Should probably
@@ -515,11 +498,6 @@ static irqreturn_t cd2401_tx_interrupt(int irq, void *dev_id)
	/* determine the channel and change to that context */
	/* determine the channel and change to that context */
	channel = (u_short) (base_addr[CyLICR] >> 2);
	channel = (u_short) (base_addr[CyLICR] >> 2);


#ifdef CONFIG_REMOTE_DEBUG
	if (channel == DEBUG_PORT) {
		panic("TxInt on debug port!!!");
	}
#endif
	/* validate the port number (as configured and open) */
	/* validate the port number (as configured and open) */
	if ((channel < 0) || (NR_PORTS <= channel)) {
	if ((channel < 0) || (NR_PORTS <= channel)) {
		base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy);
		base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy);
@@ -634,14 +612,6 @@ static irqreturn_t cd2401_rx_interrupt(int irq, void *dev_id)
	info->last_active = jiffies;
	info->last_active = jiffies;
	save_cnt = char_count = base_addr[CyRFOC];
	save_cnt = char_count = base_addr[CyRFOC];


#ifdef CONFIG_REMOTE_DEBUG
	if (channel == DEBUG_PORT) {
		while (char_count--) {
			data = base_addr[CyRDR];
			queueDebugChar(data);
		}
	} else
#endif
		/* if there is nowhere to put the data, discard it */
		/* if there is nowhere to put the data, discard it */
	if (info->tty == 0) {
	if (info->tty == 0) {
		while (char_count--) {
		while (char_count--) {
@@ -2195,9 +2165,7 @@ static int __init serial167_init(void)
		port_num++;
		port_num++;
		info++;
		info++;
	}
	}
#ifdef CONFIG_REMOTE_DEBUG

	debug_setup();
#endif
	ret = request_irq(MVME167_IRQ_SER_ERR, cd2401_rxerr_interrupt, 0,
	ret = request_irq(MVME167_IRQ_SER_ERR, cd2401_rxerr_interrupt, 0,
			  "cd2401_errors", cd2401_rxerr_interrupt);
			  "cd2401_errors", cd2401_rxerr_interrupt);
	if (ret) {
	if (ret) {
@@ -2518,193 +2486,4 @@ static int __init serial167_console_init(void)


console_initcall(serial167_console_init);
console_initcall(serial167_console_init);


#ifdef CONFIG_REMOTE_DEBUG
void putDebugChar(int c)
{
	volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
	unsigned long flags;
	volatile u_char sink;
	u_char ier;
	int port;

	local_irq_save(flags);

	/* Ensure transmitter is enabled! */

	port = DEBUG_PORT;
	base_addr[CyCAR] = (u_char) port;
	while (base_addr[CyCCR])
		;
	base_addr[CyCCR] = CyENB_XMTR;

	ier = base_addr[CyIER];
	base_addr[CyIER] = CyTxMpty;

	while (1) {
		if (pcc2chip[PccSCCTICR] & 0x20) {
			/* We have a Tx int. Acknowledge it */
			sink = pcc2chip[PccTPIACKR];
			if ((base_addr[CyLICR] >> 2) == port) {
				base_addr[CyTDR] = c;
				base_addr[CyTEOIR] = 0;
				break;
			} else
				base_addr[CyTEOIR] = CyNOTRANS;
		}
	}

	base_addr[CyIER] = ier;

	local_irq_restore(flags);
}

int getDebugChar()
{
	volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
	unsigned long flags;
	volatile u_char sink;
	u_char ier;
	int port;
	int i, c;

	i = debugiq.out;
	if (i != debugiq.in) {
		c = debugiq.buf[i];
		if (++i == DEBUG_LEN)
			i = 0;
		debugiq.out = i;
		return c;
	}
	/* OK, nothing in queue, wait in poll loop */

	local_irq_save(flags);

	/* Ensure receiver is enabled! */

	port = DEBUG_PORT;
	base_addr[CyCAR] = (u_char) port;
#if 0
	while (base_addr[CyCCR])
		;
	base_addr[CyCCR] = CyENB_RCVR;
#endif
	ier = base_addr[CyIER];
	base_addr[CyIER] = CyRxData;

	while (1) {
		if (pcc2chip[PccSCCRICR] & 0x20) {
			/* We have a Rx int. Acknowledge it */
			sink = pcc2chip[PccRPIACKR];
			if ((base_addr[CyLICR] >> 2) == port) {
				int cnt = base_addr[CyRFOC];
				while (cnt-- > 0) {
					c = base_addr[CyRDR];
					if (c == 0)
						printk
						    ("!! debug char is null (cnt=%d) !!",
						     cnt);
					else
						queueDebugChar(c);
				}
				base_addr[CyREOIR] = 0;
				i = debugiq.out;
				if (i == debugiq.in)
					panic("Debug input queue empty!");
				c = debugiq.buf[i];
				if (++i == DEBUG_LEN)
					i = 0;
				debugiq.out = i;
				break;
			} else
				base_addr[CyREOIR] = CyNOTRANS;
		}
	}

	base_addr[CyIER] = ier;

	local_irq_restore(flags);

	return (c);
}

void queueDebugChar(int c)
{
	int i;

	i = debugiq.in;
	debugiq.buf[i] = c;
	if (++i == DEBUG_LEN)
		i = 0;
	if (i != debugiq.out)
		debugiq.in = i;
}

static void debug_setup()
{
	unsigned long flags;
	volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
	int i, cflag;

	cflag = B19200;

	local_irq_save(flags);

	for (i = 0; i < 4; i++) {
		base_addr[CyCAR] = i;
		base_addr[CyLICR] = i << 2;
	}

	debugiq.in = debugiq.out = 0;

	base_addr[CyCAR] = DEBUG_PORT;

	/* baud rate */
	i = cflag & CBAUD;

	base_addr[CyIER] = 0;

	base_addr[CyCMR] = CyASYNC;
	base_addr[CyLICR] = DEBUG_PORT << 2;
	base_addr[CyLIVR] = 0x5c;

	/* tx and rx baud rate */

	base_addr[CyTCOR] = baud_co[i];
	base_addr[CyTBPR] = baud_bpr[i];
	base_addr[CyRCOR] = baud_co[i] >> 5;
	base_addr[CyRBPR] = baud_bpr[i];

	/* set line characteristics  according configuration */

	base_addr[CySCHR1] = 0;
	base_addr[CySCHR2] = 0;
	base_addr[CySCRL] = 0;
	base_addr[CySCRH] = 0;
	base_addr[CyCOR1] = Cy_8_BITS | CyPARITY_NONE;
	base_addr[CyCOR2] = 0;
	base_addr[CyCOR3] = Cy_1_STOP;
	base_addr[CyCOR4] = baud_cor4[i];
	base_addr[CyCOR5] = 0;
	base_addr[CyCOR6] = 0;
	base_addr[CyCOR7] = 0;

	write_cy_cmd(base_addr, CyINIT_CHAN);
	write_cy_cmd(base_addr, CyENB_RCVR);

	base_addr[CyCAR] = DEBUG_PORT;	/* !!! Is this needed? */

	base_addr[CyRTPRL] = 2;
	base_addr[CyRTPRH] = 0;

	base_addr[CyMSVR1] = CyRTS;
	base_addr[CyMSVR2] = CyDTR;

	base_addr[CyIER] = CyRxData;

	local_irq_restore(flags);

}				/* debug_setup */

#endif

MODULE_LICENSE("GPL");
MODULE_LICENSE("GPL");
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