ath9k_hw: add register definitions for the new ANI

#define AR_PHY_FIND_SIG_FIRPWR    0x03FC0000

#define AR_PHY_FIND_SIG_FIRPWR_S  18

#define AR_PHY_FIND_SIG_LOW           0x9840

#define AR_PHY_FIND_SIG_FIRSTEP_LOW   0x00000FC0L

#define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6

#define AR_PHY_AGC_CTL1                  0x985C

#define AR_PHY_AGC_CTL1_COARSE_LOW       0x00007F80

#define AR_PHY_AGC_CTL1_COARSE_LOW_S     7

#define AR_PHY_EXT_CCA_CYCPWR_THR1_S    9

#define AR_PHY_EXT_CCA_THRESH62         0x007F0000

#define AR_PHY_EXT_CCA_THRESH62_S       16

#define AR_PHY_EXT_TIMING5_CYCPWR_THR1   0x0000FE00L

#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9

#define AR_PHY_EXT_MINCCA_PWR           0xFF800000

#define AR_PHY_EXT_MINCCA_PWR_S         23

#define AR9280_PHY_EXT_MINCCA_PWR       0x01FF0000

#define AR_PHY_EXT_CCA_THRESH62_S       16

#define AR_PHY_EXT_MINCCA_PWR   0x01FF0000

#define AR_PHY_EXT_MINCCA_PWR_S 16

#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L

#define AR_PHY_EXT_CYCPWR_THR1_S 9

#define AR_PHY_TIMING5_CYCPWR_THR1  0x000000FE

#define AR_PHY_TIMING5_CYCPWR_THR1_S    1

#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE  0x00000001

#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ                           0x1ffffe00

#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S                                  9

#define AR_PHY_MRC_CCK_CTRL         (AR_AGC_BASE + 0x1d0)

#define AR_PHY_MRC_CCK_ENABLE       0x00000001

#define AR_PHY_MRC_CCK_ENABLE_S              0

#define AR_PHY_MRC_CCK_MUX_REG      0x00000002

#define AR_PHY_MRC_CCK_MUX_REG_S             1

#define AR_PHY_RX_OCGAIN        (AR_AGC_BASE + 0x200)

#define AR_PHY_CCA_NOM_VAL_9300_2GHZ          -110