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Commit 7c481da6 authored by Suresh Vankadara's avatar Suresh Vankadara Committed by Gerrit - the friendly Code Review server
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Merge changes I5c667e43,Ia82a8b6e into dev/msm-4.14-camx 

* changes:
  msm: cam: isp: Add ubwc support for sdmmagpie ife
  msm: camera: cpas: Add support for sdmmagpie cpas
parents 0ccc5d3c 982ae87e

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c

+8 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "cpastop_v170_110.h"

#include "cpastop_v175_100.h"

#include "cpastop_v175_101.h"

#include "cpastop_v175_120.h"



struct cam_camnoc_info *camnoc_info;
@@ -105,6 +106,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, 
			(hw_caps->cpas_version.minor == 0) &&

			(hw_caps->cpas_version.incr == 1))

			soc_info->hw_version = CAM_CPAS_TITAN_175_V101;

		else if ((hw_caps->cpas_version.major == 1) &&

			(hw_caps->cpas_version.minor == 2) &&

			(hw_caps->cpas_version.incr == 0))

			soc_info->hw_version = CAM_CPAS_TITAN_175_V120;

	} else if ((hw_caps->camera_version.major == 1) &&

		(hw_caps->camera_version.minor == 5) &&

		(hw_caps->camera_version.incr == 0)) {
@@ -587,6 +592,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, 
	case CAM_CPAS_TITAN_175_V101:

		camnoc_info = &cam175_cpas101_camnoc_info;

		break;

	case CAM_CPAS_TITAN_175_V120:

		camnoc_info = &cam175_cpas120_camnoc_info;

		break;

	case CAM_CPAS_TITAN_150_V100:

		camnoc_info = &cam150_cpas100_camnoc_info;

		break;

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h

+19 −0
Original line number Diff line number Diff line
@@ -36,6 +36,10 @@ 
 * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error

 *                                               detected in the IPE/BPS UBWC

 *                                               encoder instance

 * @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR:    Triggered if any UBWC error

 *                                               is detected in IFE0 write path

 * @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR:  Triggered if any UBWC error

 *                                               is detected in IFE1 write path

 * @CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT              : Triggered when the QHS_ICP

 *                                               slave  times out after 4000

 *                                               AHB cycles
@@ -50,6 +54,10 @@ enum cam_camnoc_hw_irq_type { 
		CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR =

		CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR =
@@ -69,10 +77,16 @@ enum cam_camnoc_hw_irq_type { 
 * @CAM_CAMNOC_CDM: Indicates CDM HW connection to camnoc

 * @CAM_CAMNOC_IFE02: Indicates IFE0, IFE2 HW connection to camnoc

 * @CAM_CAMNOC_IFE13: Indicates IFE1, IFE3 HW connection to camnoc

 * @CAM_CAMNOC_IFE0123_RDI_WRITE: RDI write only for all IFEx

 * @CAM_CAMNOC_IFE0_NRDI_WRITE: IFE0 non-RDI write

 * @CAM_CAMNOC_IFE01_RDI_READ: IFE0/1 RDI READ

 * @CAM_CAMNOC_IFE1_NRDI_WRITE: IFE1 non-RDI write

 * @CAM_CAMNOC_IPE_BPS_LRME_READ: Indicates IPE, BPS, LRME Read HW

 *         connection to camnoc

 * @CAM_CAMNOC_IPE_BPS_LRME_WRITE: Indicates IPE, BPS, LRME Write HW

 *         connection to camnoc

 * @CAM_CAMNOC_IPE_VID_DISP_WRITE: Indicates IPE's VID/DISP Wrire HW

 *         connection to camnoc

 * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc

 * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc

 * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc
@@ -81,8 +95,13 @@ enum cam_camnoc_port_type { 
	CAM_CAMNOC_CDM,

	CAM_CAMNOC_IFE02,

	CAM_CAMNOC_IFE13,

	CAM_CAMNOC_IFE0123_RDI_WRITE,

	CAM_CAMNOC_IFE0_NRDI_WRITE,

	CAM_CAMNOC_IFE01_RDI_READ,

	CAM_CAMNOC_IFE1_NRDI_WRITE,

	CAM_CAMNOC_IPE_BPS_LRME_READ,

	CAM_CAMNOC_IPE_BPS_LRME_WRITE,

	CAM_CAMNOC_IPE_VID_DISP_WRITE,

	CAM_CAMNOC_JPEG,

	CAM_CAMNOC_FD,

	CAM_CAMNOC_ICP,

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_120.h

0 → 100644
+730 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CPASTOP_V175_120_H_

#define _CPASTOP_V175_120_H_



#define TEST_IRQ_ENABLE 0



static struct cam_camnoc_irq_sbm cam_cpas_v175_120_irq_sbm = {

	.sbm_enable = {

		.access_type = CAM_REG_TYPE_READ_WRITE,

		.enable = true,

		.offset = 0x2240, /* SBM_FAULTINEN0_LOW */

		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/

			0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */

			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */

			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */

			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */

			0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */

			(TEST_IRQ_ENABLE ?

			0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */

			0x0),

	},

	.sbm_status = {

		.access_type = CAM_REG_TYPE_READ,

		.enable = true,

		.offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */

	},

	.sbm_clear = {

		.access_type = CAM_REG_TYPE_WRITE,

		.enable = true,

		.offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */

		.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,

	}

};



static struct cam_camnoc_irq_err

	cam_cpas_v175_120_irq_err[] = {

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,

		.enable = true,

		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x3Ba0, /* SPECIFIC_IFE02_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x3B90, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x3B98, /* SPECIFIC_IFE02_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x55a0, /* SPECIFIC_IFE13_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x5590, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x5598, /* SPECIFIC_IFE13_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,

		.enable = true,

		.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2Ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2B90,

			/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,

		.enable = true,

		.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */

			.value = 0x1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */

		},

		.err_clear = {

			.enable = false,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,

		.enable = false,

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,

		.enable = false,

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,

		.enable = TEST_IRQ_ENABLE ? true : false,

		.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */

			.value = 0x5,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */

		},

		.err_clear = {

			.enable = false,

		},

	},

};



static struct cam_camnoc_specific

	cam_cpas_v175_120_camnoc_specific[] = {

	{

		.port_type = CAM_CAMNOC_CDM,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			/* cdm_main_SpecificToNttpTr_Urgency_Low */

			.offset = 0x4238,

			.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */

			.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */

			.value = 0x2,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE0123_RDI_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IFE0123_PRIORITYLUT_LOW */

			.offset = 0x3630,

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */

			.offset = 0x3634,

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */

			/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */

			.value = 0xF,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE0_NRDI_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */

			/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */

			.value = 0xF,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */

			.value = 1,

		},

	},

	{

		/* IFE0/1 RDI READ PATH */

		.port_type = CAM_CAMNOC_IFE01_RDI_READ,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */

			.value = 0x44443333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */

			.value = 0x66665555,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */

			/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */

			.mask = 0x7,

			/* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x0,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */

			.value = 0xF,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE1_NRDI_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */

			.offset = 0x5434,

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */

			/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */

			.value = 0xF,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */

			.value = 1,

		},

	},

	{

		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */

			.mask = 0x7,

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */

			.shift = 0x0,

			.value = 0x3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */

			.value = 1,

		},

	},

	{

		.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x2E38, /* SPECIFIC_IBL_WR_URGENCY_LOW */

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 0x3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

			.value = 0,

		},

	},

	{

		.port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */

			.offset = 0x5E30,

			.value = 0x33330000,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */

			.offset = 0x5E34,

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */

			.offset = 0x5E38,

			/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */

			.mask = 0x70,

			/* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */

			.offset = 0x5E40,

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */

			.offset = 0x5E48,

			.value = 0x0,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

			.value = 1,

		},

	},



	{

		.port_type = CAM_CAMNOC_JPEG,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */

			.value = 0x22,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_FD,

		.enable = false,

	},

	{

		/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/

		.port_type = CAM_CAMNOC_ICP,

		.enable = true,

		.flag_out_set0_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_WRITE,

			.masked_value = 0,

			.offset = 0x2288,

			.value = 0x100000,

		},

	},

};



static struct cam_camnoc_err_logger_info cam175_cpas120_err_logger_offsets = {

	.mainctrl     =  0x4F08, /* ERRLOGGER_MAINCTL_LOW */

	.errvld       =  0x4F10, /* ERRLOGGER_ERRVLD_LOW */

	.errlog0_low  =  0x4F20, /* ERRLOGGER_ERRLOG0_LOW */

	.errlog0_high =  0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */

	.errlog1_low  =  0x4F28, /* ERRLOGGER_ERRLOG1_LOW */

	.errlog1_high =  0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */

	.errlog2_low  =  0x4F30, /* ERRLOGGER_ERRLOG2_LOW */

	.errlog2_high =  0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */

	.errlog3_low  =  0x4F38, /* ERRLOGGER_ERRLOG3_LOW */

	.errlog3_high =  0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */

};



static struct cam_cpas_hw_errata_wa_list cam175_cpas120_errata_wa_list = {

	.camnoc_flush_slave_pending_trans = {

		.enable = false,

		.data.reg_info = {

			.access_type = CAM_REG_TYPE_READ,

			.offset = 0x2300, /* SidebandManager_SenseIn0_Low */

			.mask = 0xE0000, /* Bits 17, 18, 19 */

			.value = 0, /* expected to be 0 */

		},

	},

};



static struct cam_camnoc_info cam175_cpas120_camnoc_info = {

	.specific = &cam_cpas_v175_120_camnoc_specific[0],

	.specific_size = sizeof(cam_cpas_v175_120_camnoc_specific) /

		sizeof(cam_cpas_v175_120_camnoc_specific[0]),

	.irq_sbm = &cam_cpas_v175_120_irq_sbm,

	.irq_err = &cam_cpas_v175_120_irq_err[0],

	.irq_err_size = sizeof(cam_cpas_v175_120_irq_err) /

		sizeof(cam_cpas_v175_120_irq_err[0]),

	.err_logger = &cam175_cpas120_err_logger_offsets,

	.errata_wa_list = &cam175_cpas120_errata_wa_list,

};



#endif /* _CPASTOP_V175_120_H_ */

drivers/media/platform/msm/camera/cam_cpas/include/cam_cpas_api.h

+8 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ enum cam_cpas_hw_version { 
	CAM_CPAS_TITAN_170_V120 = 0x170120,

	CAM_CPAS_TITAN_175_V100 = 0x175100,

	CAM_CPAS_TITAN_175_V101 = 0x175101,

	CAM_CPAS_TITAN_175_V120 = 0x175120,

	CAM_CPAS_TITAN_MAX

};
@@ -64,6 +65,11 @@ enum cam_cpas_hw_version { 
 * @CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE1 or IFE3 UBWC encoder

 *                                            instance

 * @CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR   : Triggered if any error detected

 *                                            in the IFE0 UBWC encoder instance

 * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE1 UBWC encoder

 *                                            instance

 * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error detected

 *                                            in the IPE/BPS UBWC decoder

 *                                            instance
@@ -77,6 +83,8 @@ enum cam_camnoc_irq_type { 
	CAM_CAMNOC_IRQ_SLAVE_ERROR,

	CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,

	CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_AHB_TIMEOUT,

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c

+2 −0
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ static bool cam_vfe_cpas_cb(uint32_t client_handle, void *userdata, 
	switch (irq_data->irq_type) {

	case CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR:

	case CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR:

	case CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR:

	case CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR:

		CAM_ERR_RATE_LIMIT(CAM_ISP,

			"IFE UBWC Encode error type=%d status=%x",

			irq_data->irq_type,