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Commit 7bb103a6 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: npucc: Update NPU Q6 frequency for ATOLL 



As per the hardware recommendation update the q6 PLL to use double the
frequency and use the RCG pre divider.

Change-Id: Ic9ebafa881046d8b0155674fe97ae63a5598e466
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent bf6c49bc

drivers/clk/qcom/npucc-atoll.c

+8 −8
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -357,13 +357,13 @@ static struct clk_rcg2 npu_cc_core_clk_src = { 
};



static const struct freq_tbl ftbl_npu_dsp_core_clk_src[] = {

	F(250000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(300000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(400000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(500000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(600000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(660000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(800000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0),

	F(250000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(300000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(400000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(500000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(600000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(660000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	F(800000000, P_NPU_Q6SS_PLL_OUT_MAIN, 2, 0, 0),

	{ }

};