clk: qcom: npucc-sdm855: Update the frequency table for NPU cal_dp RCG



The frequency configuration recommendation for the
npu_cc_cal_dp_clk_src RCG has been updated. Reflect
the same in the clock driver.

Change-Id: I715e7fe4d5526c72e544f80df239d4a9719b63ae
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

parent 0f7ebf1c

drivers/clk/qcom/npucc-sdm855.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -164,7 +164,7 @@ static struct clk_alpha_pll_postdiv npu_cc_pll1_out_even = {
		};

		static const struct freq_tbl ftbl_npu_cc_cal_dp_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		F(350000000, P_NPU_CC_PLL1_OUT_EVEN, 2, 0, 0),
		F(400000000, P_NPU_CC_PLL0_OUT_EVEN, 3, 0, 0),