Loading drivers/gpu/drm/msm/sde/sde_encoder.c +23 −3 Original line number Diff line number Diff line Loading @@ -371,6 +371,24 @@ static int _sde_encoder_get_mode_info(struct drm_encoder *drm_enc, return sde_connector_get_mode_info(conn_state, mode_info); } static bool _sde_encoder_is_autorefresh_enabled( struct sde_encoder_virt *sde_enc) { struct drm_connector *drm_conn; if (!sde_enc->cur_master || !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE)) return false; drm_conn = sde_enc->cur_master->connector; if (!drm_conn || !drm_conn->state) return false; return sde_connector_get_property(drm_conn->state, CONNECTOR_PROP_AUTOREFRESH) ? true : false; } static bool _sde_encoder_is_dsc_enabled(struct drm_encoder *drm_enc) { struct msm_compression_info *comp_info; Loading Loading @@ -3865,7 +3883,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) u32 pending_kickoff_cnt; struct msm_drm_private *priv = NULL; struct sde_kms *sde_kms = NULL; bool is_vid_mode = false; bool is_regdma_blocking = false, is_vid_mode = false; if (!sde_enc) { SDE_ERROR("invalid encoder\n"); Loading @@ -3874,6 +3892,8 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) is_vid_mode = sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_VID_MODE; is_regdma_blocking = (is_vid_mode || _sde_encoder_is_autorefresh_enabled(sde_enc)); /* don't perform flush/start operations for slave encoders */ for (i = 0; i < sde_enc->num_phys_encs; i++) { Loading Loading @@ -3902,7 +3922,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) if (!phys->ops.needs_single_flush || !phys->ops.needs_single_flush(phys)) { if (ctl->ops.reg_dma_flush) ctl->ops.reg_dma_flush(ctl, is_vid_mode); ctl->ops.reg_dma_flush(ctl, is_regdma_blocking); _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0); } else if (ctl->ops.get_pending_flush) { ctl->ops.get_pending_flush(ctl, &pending_flush); Loading @@ -3913,7 +3933,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) if (pending_flush.pending_flush_mask && sde_enc->cur_master) { ctl = sde_enc->cur_master->hw_ctl; if (ctl->ops.reg_dma_flush) ctl->ops.reg_dma_flush(ctl, is_vid_mode); ctl->ops.reg_dma_flush(ctl, is_regdma_blocking); _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master, &pending_flush); } Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +23 −3 Original line number Diff line number Diff line Loading @@ -371,6 +371,24 @@ static int _sde_encoder_get_mode_info(struct drm_encoder *drm_enc, return sde_connector_get_mode_info(conn_state, mode_info); } static bool _sde_encoder_is_autorefresh_enabled( struct sde_encoder_virt *sde_enc) { struct drm_connector *drm_conn; if (!sde_enc->cur_master || !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE)) return false; drm_conn = sde_enc->cur_master->connector; if (!drm_conn || !drm_conn->state) return false; return sde_connector_get_property(drm_conn->state, CONNECTOR_PROP_AUTOREFRESH) ? true : false; } static bool _sde_encoder_is_dsc_enabled(struct drm_encoder *drm_enc) { struct msm_compression_info *comp_info; Loading Loading @@ -3865,7 +3883,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) u32 pending_kickoff_cnt; struct msm_drm_private *priv = NULL; struct sde_kms *sde_kms = NULL; bool is_vid_mode = false; bool is_regdma_blocking = false, is_vid_mode = false; if (!sde_enc) { SDE_ERROR("invalid encoder\n"); Loading @@ -3874,6 +3892,8 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) is_vid_mode = sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_VID_MODE; is_regdma_blocking = (is_vid_mode || _sde_encoder_is_autorefresh_enabled(sde_enc)); /* don't perform flush/start operations for slave encoders */ for (i = 0; i < sde_enc->num_phys_encs; i++) { Loading Loading @@ -3902,7 +3922,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) if (!phys->ops.needs_single_flush || !phys->ops.needs_single_flush(phys)) { if (ctl->ops.reg_dma_flush) ctl->ops.reg_dma_flush(ctl, is_vid_mode); ctl->ops.reg_dma_flush(ctl, is_regdma_blocking); _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0); } else if (ctl->ops.get_pending_flush) { ctl->ops.get_pending_flush(ctl, &pending_flush); Loading @@ -3913,7 +3933,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc) if (pending_flush.pending_flush_mask && sde_enc->cur_master) { ctl = sde_enc->cur_master->hw_ctl; if (ctl->ops.reg_dma_flush) ctl->ops.reg_dma_flush(ctl, is_vid_mode); ctl->ops.reg_dma_flush(ctl, is_regdma_blocking); _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master, &pending_flush); } Loading