Loading drivers/gpu/msm/adreno.c +13 −13 Original line number Diff line number Diff line Loading @@ -1832,13 +1832,13 @@ static int _adreno_start(struct adreno_device *adreno_dev) } /* Send OOB request to turn on the GX */ if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { status = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (status) goto error_mmu_off; } if (gmu_dev_ops->hfi_start_msg) { if (GMU_DEV_OP_VALID(gmu_dev_ops, hfi_start_msg)) { status = gmu_dev_ops->hfi_start_msg(adreno_dev); if (status) goto error_oob_clear; Loading Loading @@ -2028,7 +2028,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) pmqos_active_vote); /* Send OOB request to allow IFPC */ if (gmu_dev_ops->oob_clear) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) { gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); /* If we made it this far, the BOOT OOB was sent to the GMU */ Loading @@ -2039,7 +2039,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) return 0; error_oob_clear: if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); error_mmu_off: Loading Loading @@ -2092,9 +2092,9 @@ static int adreno_stop(struct kgsl_device *device) return 0; /* Turn the power on one last time before stopping */ if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { error = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (error) { if (error && GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) { gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); if (gmu_core_regulator_isenabled(device)) { /* GPU is on. Try recovery */ Loading Loading @@ -2128,7 +2128,7 @@ static int adreno_stop(struct kgsl_device *device) /* Save physical performance counter values before GPU power down*/ adreno_perfcounter_save(adreno_dev); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); /* Loading @@ -2137,7 +2137,7 @@ static int adreno_stop(struct kgsl_device *device) * GMU to return to the lowest idle level. This is * because some idle level transitions require VBIF and MMU. */ if (!error && gmu_dev_ops->wait_for_lowest_idle && if (!error && GMU_DEV_OP_VALID(gmu_dev_ops, wait_for_lowest_idle) && gmu_dev_ops->wait_for_lowest_idle(adreno_dev)) { gmu_core_setbit(device, GMU_FAULT); Loading Loading @@ -2789,7 +2789,7 @@ int adreno_soft_reset(struct kgsl_device *device) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); int ret; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { ret = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (ret) return ret; Loading @@ -2813,7 +2813,7 @@ int adreno_soft_reset(struct kgsl_device *device) else ret = _soft_reset(adreno_dev); if (ret) { if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); return ret; } Loading Loading @@ -2867,7 +2867,7 @@ int adreno_soft_reset(struct kgsl_device *device) /* Restore physical performance counter values after soft reset */ adreno_perfcounter_restore(adreno_dev); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); return ret; Loading Loading @@ -3215,7 +3215,7 @@ unsigned int adreno_gmu_ifpc_show(struct adreno_device *adreno_dev) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->ifpc_show) if (GMU_DEV_OP_VALID(gmu_dev_ops, ifpc_show)) return gmu_dev_ops->ifpc_show(adreno_dev); return 0; Loading @@ -3226,7 +3226,7 @@ int adreno_gmu_ifpc_store(struct adreno_device *adreno_dev, unsigned int val) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->ifpc_store) if (GMU_DEV_OP_VALID(gmu_dev_ops, ifpc_store)) return gmu_dev_ops->ifpc_store(adreno_dev, val); return -EINVAL; Loading drivers/gpu/msm/adreno.h +2 −2 Original line number Diff line number Diff line Loading @@ -1869,7 +1869,7 @@ static inline int adreno_perfcntr_active_oob_get( if (ret) return ret; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { ret = gmu_dev_ops->oob_set(adreno_dev, oob_perfcntr); if (ret) kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); Loading @@ -1884,7 +1884,7 @@ static inline void adreno_perfcntr_active_oob_put( struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_perfcntr); kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); Loading drivers/gpu/msm/adreno_a6xx.c +5 −2 Original line number Diff line number Diff line Loading @@ -917,7 +917,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) * 3. HFI * At this point, we are guaranteed all. */ if (gmu_dev_ops->enable_lm) if (GMU_DEV_OP_VALID(gmu_dev_ops, enable_lm)) gmu_dev_ops->enable_lm(device); } Loading Loading @@ -1336,7 +1336,10 @@ static int a6xx_microcode_read(struct adreno_device *adreno_dev) return ret; } if (GMU_DEV_OP_VALID(gmu_dev_ops, load_firmware)) return gmu_dev_ops->load_firmware(device); return 0; } static int a6xx_soft_reset(struct adreno_device *adreno_dev) Loading drivers/gpu/msm/adreno_a6xx_preempt.c +2 −2 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) if (in_interrupt() == 0) { int status; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { status = gmu_dev_ops->oob_set(adreno_dev, oob_preempt); if (status) return; Loading Loading @@ -75,7 +75,7 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) spin_unlock_irqrestore(&rb->preempt_lock, flags); if (in_interrupt() == 0) { if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_preempt); } } Loading drivers/gpu/msm/adreno_a6xx_snapshot.c +1 −1 Original line number Diff line number Diff line Loading @@ -1498,7 +1498,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, unsigned int i; /* GMU TCM data dumped through AHB */ if (gmu_dev_ops->snapshot) if (GMU_DEV_OP_VALID(gmu_dev_ops, snapshot)) gmu_dev_ops->snapshot(adreno_dev, snapshot); sptprac_on = gpudev->sptprac_is_on(adreno_dev); Loading Loading
drivers/gpu/msm/adreno.c +13 −13 Original line number Diff line number Diff line Loading @@ -1832,13 +1832,13 @@ static int _adreno_start(struct adreno_device *adreno_dev) } /* Send OOB request to turn on the GX */ if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { status = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (status) goto error_mmu_off; } if (gmu_dev_ops->hfi_start_msg) { if (GMU_DEV_OP_VALID(gmu_dev_ops, hfi_start_msg)) { status = gmu_dev_ops->hfi_start_msg(adreno_dev); if (status) goto error_oob_clear; Loading Loading @@ -2028,7 +2028,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) pmqos_active_vote); /* Send OOB request to allow IFPC */ if (gmu_dev_ops->oob_clear) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) { gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); /* If we made it this far, the BOOT OOB was sent to the GMU */ Loading @@ -2039,7 +2039,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) return 0; error_oob_clear: if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); error_mmu_off: Loading Loading @@ -2092,9 +2092,9 @@ static int adreno_stop(struct kgsl_device *device) return 0; /* Turn the power on one last time before stopping */ if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { error = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (error) { if (error && GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) { gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); if (gmu_core_regulator_isenabled(device)) { /* GPU is on. Try recovery */ Loading Loading @@ -2128,7 +2128,7 @@ static int adreno_stop(struct kgsl_device *device) /* Save physical performance counter values before GPU power down*/ adreno_perfcounter_save(adreno_dev); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); /* Loading @@ -2137,7 +2137,7 @@ static int adreno_stop(struct kgsl_device *device) * GMU to return to the lowest idle level. This is * because some idle level transitions require VBIF and MMU. */ if (!error && gmu_dev_ops->wait_for_lowest_idle && if (!error && GMU_DEV_OP_VALID(gmu_dev_ops, wait_for_lowest_idle) && gmu_dev_ops->wait_for_lowest_idle(adreno_dev)) { gmu_core_setbit(device, GMU_FAULT); Loading Loading @@ -2789,7 +2789,7 @@ int adreno_soft_reset(struct kgsl_device *device) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); int ret; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { ret = gmu_dev_ops->oob_set(adreno_dev, oob_gpu); if (ret) return ret; Loading @@ -2813,7 +2813,7 @@ int adreno_soft_reset(struct kgsl_device *device) else ret = _soft_reset(adreno_dev); if (ret) { if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); return ret; } Loading Loading @@ -2867,7 +2867,7 @@ int adreno_soft_reset(struct kgsl_device *device) /* Restore physical performance counter values after soft reset */ adreno_perfcounter_restore(adreno_dev); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_gpu); return ret; Loading Loading @@ -3215,7 +3215,7 @@ unsigned int adreno_gmu_ifpc_show(struct adreno_device *adreno_dev) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->ifpc_show) if (GMU_DEV_OP_VALID(gmu_dev_ops, ifpc_show)) return gmu_dev_ops->ifpc_show(adreno_dev); return 0; Loading @@ -3226,7 +3226,7 @@ int adreno_gmu_ifpc_store(struct adreno_device *adreno_dev, unsigned int val) struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->ifpc_store) if (GMU_DEV_OP_VALID(gmu_dev_ops, ifpc_store)) return gmu_dev_ops->ifpc_store(adreno_dev, val); return -EINVAL; Loading
drivers/gpu/msm/adreno.h +2 −2 Original line number Diff line number Diff line Loading @@ -1869,7 +1869,7 @@ static inline int adreno_perfcntr_active_oob_get( if (ret) return ret; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { ret = gmu_dev_ops->oob_set(adreno_dev, oob_perfcntr); if (ret) kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); Loading @@ -1884,7 +1884,7 @@ static inline void adreno_perfcntr_active_oob_put( struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS( KGSL_DEVICE(adreno_dev)); if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_perfcntr); kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); Loading
drivers/gpu/msm/adreno_a6xx.c +5 −2 Original line number Diff line number Diff line Loading @@ -917,7 +917,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) * 3. HFI * At this point, we are guaranteed all. */ if (gmu_dev_ops->enable_lm) if (GMU_DEV_OP_VALID(gmu_dev_ops, enable_lm)) gmu_dev_ops->enable_lm(device); } Loading Loading @@ -1336,7 +1336,10 @@ static int a6xx_microcode_read(struct adreno_device *adreno_dev) return ret; } if (GMU_DEV_OP_VALID(gmu_dev_ops, load_firmware)) return gmu_dev_ops->load_firmware(device); return 0; } static int a6xx_soft_reset(struct adreno_device *adreno_dev) Loading
drivers/gpu/msm/adreno_a6xx_preempt.c +2 −2 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) if (in_interrupt() == 0) { int status; if (gmu_dev_ops->oob_set) { if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_set)) { status = gmu_dev_ops->oob_set(adreno_dev, oob_preempt); if (status) return; Loading Loading @@ -75,7 +75,7 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) spin_unlock_irqrestore(&rb->preempt_lock, flags); if (in_interrupt() == 0) { if (gmu_dev_ops->oob_clear) if (GMU_DEV_OP_VALID(gmu_dev_ops, oob_clear)) gmu_dev_ops->oob_clear(adreno_dev, oob_preempt); } } Loading
drivers/gpu/msm/adreno_a6xx_snapshot.c +1 −1 Original line number Diff line number Diff line Loading @@ -1498,7 +1498,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, unsigned int i; /* GMU TCM data dumped through AHB */ if (gmu_dev_ops->snapshot) if (GMU_DEV_OP_VALID(gmu_dev_ops, snapshot)) gmu_dev_ops->snapshot(adreno_dev, snapshot); sptprac_on = gpudev->sptprac_is_on(adreno_dev); Loading