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Commit 77bac1e1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: Enable HMP for SA8195, SA8155 and SA6155 VM"

parents 2bc88431 ba64d102

arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi

+100 −0
Original line number Diff line number Diff line
@@ -23,6 +23,106 @@ 
	qcom,msm-name = "SA6155P";

	qcom,msm-id = <377 0x0>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			capacity-dmips-mhz = <1024>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			capacity-dmips-mhz = <1024>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			capacity-dmips-mhz = <347>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			capacity-dmips-mhz = <347>;

		};



		CPU4: cpu@4 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x4>;

			capacity-dmips-mhz = <347>;

		};



		CPU5: cpu@5 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x5>;

			capacity-dmips-mhz = <347>;

		};



		CPU6: cpu@6 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x6>;

			capacity-dmips-mhz = <347>;

		};



		CPU7: cpu@7 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x7>;

			capacity-dmips-mhz = <347>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};



				core1 {

					cpu = <&CPU1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU2>;

				};



				core1 {

					cpu = <&CPU3>;

				};



				core2 {

					cpu = <&CPU4>;

				};



				core3 {

					cpu = <&CPU5>;

				};



				core4 {

					cpu = <&CPU6>;

				};



				core5 {

					cpu = <&CPU7>;

				};

			};

		};

	};





	aliases {

		pci-domain0 = &pcie0; /* PCIe0 domain */

	};

arch/arm64/boot/dts/qcom/sa8155-vm-la-mt.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
			label = "pmem_shared_mem";

		};

	};



	/delete-node/ cpus;

};



&slpi_tlmm {

arch/arm64/boot/dts/qcom/sa8155-vm-lv-mt.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
			label = "pmem_shared_mem";

		};

	};



	/delete-node/ cpus;

};



&hab {

arch/arm64/boot/dts/qcom/sa8155-vm.dtsi

+101 −0
Original line number Diff line number Diff line
@@ -16,6 +16,107 @@ 
	qcom,msm-name = "SA8155 V2";

	qcom,msm-id = <362 0x20000>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			capacity-dmips-mhz = <1024>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			capacity-dmips-mhz = <902>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			capacity-dmips-mhz = <902>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			capacity-dmips-mhz = <902>;

		};



		CPU4: cpu@4 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x4>;

			capacity-dmips-mhz = <320>;

		};



		CPU5: cpu@5 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x5>;

			capacity-dmips-mhz = <320>;

		};



		CPU6: cpu@6 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x6>;

			capacity-dmips-mhz = <320>;

		};



		CPU7: cpu@7 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x7>;

			capacity-dmips-mhz = <320>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU1>;

				};



				core1 {

					cpu = <&CPU2>;

				};



				core2 {

					cpu = <&CPU3>;

				};

			};



			cluster2 {

				core0 {

					cpu = <&CPU4>;

				};



				core1 {

					cpu = <&CPU5>;

				};



				core2 {

					cpu = <&CPU6>;

				};



				core3 {

					cpu = <&CPU7>;

				};

			};

		};

	};



	aliases {

		pci-domain0 = &pcie0; /* PCIe0 domain */

		sdhc2 = &sdhc_2; /* SDC2 SD card slot */

arch/arm64/boot/dts/qcom/sa8195-vm-la-mt.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
		};

	};



	/delete-node/ cpus;

};



&slpi_tlmm {