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Commit 76a250f9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata 

Pull libata updates from Tejun Heo:
 "Nothing too interesting. Several patches to convert mdelay() to
  usleep_range(), removal of unused pata_at32, and other low level
  driver specific changes"

* 'for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  ata: pata_pdc2027x: Replace mdelay with msleep
  ata: pata_it821x: Replace mdelay with usleep_range in it821x_firmware_command
  ata: sata_mv: Replace mdelay with usleep_range in mv_reset_channel
  ata: remove pata_at32
  phy: brcm-sata: remove unused variable
  phy: brcm-sata: fix semicolon.cocci warnings
  ata: ahci_brcm: Recover from failures to identify devices
  phy: brcm-sata: Implement calibrate callback
  ahci: Add Intel Cannon Lake PCH-H PCI ID
  ata_piix: constify pci_bits
  libata:pata_atiixp: Don't use unconnected secondary port on SB600
  ata: ahci_brcm: Avoid clobbering SATA_TOP_CTRL_BUS_CTRL
  ahci: Allow setting a default LPM policy for mobile chipsets
  ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI
  ahci: Annotate PCI ids for mobile Intel chipsets as such
parents f8cc87b6 b3506c7e

drivers/ata/Kconfig

+19 −9
Original line number Diff line number Diff line
@@ -92,6 +92,25 @@ config SATA_AHCI 


	  If unsure, say N.



config SATA_MOBILE_LPM_POLICY

	int "Default SATA Link Power Management policy for mobile chipsets"

	range 0 4

	default 0

	depends on SATA_AHCI

	help

	  Select the Default SATA Link Power Management (LPM) policy to use

	  for mobile / laptop variants of chipsets / "South Bridges".



	  The value set has the following meanings:

		0 => Keep firmware settings

		1 => Maximum performance

		2 => Medium power

		3 => Medium power with Device Initiated PM enabled

		4 => Minimum power



	  Note "Minimum power" is known to cause issues, including disk

	  corruption, with some disks and should not be used.



config SATA_AHCI_PLATFORM

	tristate "Platform AHCI SATA support"

	help
@@ -925,15 +944,6 @@ endif # ATA_BMDMA 


comment "PIO-only SFF controllers"



config PATA_AT32

	tristate "Atmel AVR32 PATA support (Experimental)"

	depends on AVR32 && PLATFORM_AT32AP

	help

	  This option enables support for the IDE devices on the

	  Atmel AT32AP platform.



	  If unsure, say N.



config PATA_CMD640_PCI

	tristate "CMD640 PCI PATA support (Experimental)"

	depends on PCI

drivers/ata/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@ obj-$(CONFIG_PATA_VIA) += pata_via.o 
obj-$(CONFIG_PATA_WINBOND)	+= pata_sl82c105.o



# SFF PIO only

obj-$(CONFIG_PATA_AT32)		+= pata_at32.o

obj-$(CONFIG_PATA_CMD640_PCI)	+= pata_cmd640.o

obj-$(CONFIG_PATA_FALCON)	+= pata_falcon.o

obj-$(CONFIG_PATA_ISAPNP)	+= pata_isapnp.o

drivers/ata/ahci.c

+57 −37
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ enum board_ids { 
	/* board IDs by feature in alphabetical order */

	board_ahci,

	board_ahci_ign_iferr,

	board_ahci_mobile,

	board_ahci_nomsi,

	board_ahci_noncq,

	board_ahci_nosntf,
@@ -140,6 +141,13 @@ static const struct ata_port_info ahci_port_info[] = { 
		.udma_mask	= ATA_UDMA6,

		.port_ops	= &ahci_ops,

	},

	[board_ahci_mobile] = {

		AHCI_HFLAGS	(AHCI_HFLAG_IS_MOBILE),

		.flags		= AHCI_FLAG_COMMON,

		.pio_mask	= ATA_PIO4,

		.udma_mask	= ATA_UDMA6,

		.port_ops	= &ahci_ops,

	},

	[board_ahci_nomsi] = {

		AHCI_HFLAGS	(AHCI_HFLAG_NO_MSI),

		.flags		= AHCI_FLAG_COMMON,
@@ -252,13 +260,13 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */

	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */

	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */

	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */

	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */

	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */

	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */

	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
@@ -268,9 +276,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */

	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */

	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */

	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
@@ -293,9 +301,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */

	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */

	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */

	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
@@ -304,28 +312,28 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */

	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */

	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */

	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */

	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */

	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */

	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */

	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */

	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
@@ -353,26 +361,26 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */

	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */

	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */

	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */

	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */

	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */

	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */

	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */

	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */

	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */

	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */

	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */

	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */

	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */

	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */

	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/

	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
@@ -386,6 +394,11 @@ static const struct pci_device_id ahci_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/

	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/

	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/

	{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */

	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */

	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */

	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */

	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */



	/* JMicron 360/1/3/5/6, match class to avoid IDE function */

	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -593,6 +606,9 @@ static int marvell_enable = 1; 
module_param(marvell_enable, int, 0644);

MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");



static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;

module_param(mobile_lpm_policy, int, 0644);

MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");



static void ahci_pci_save_initial_config(struct pci_dev *pdev,

					 struct ahci_host_priv *hpriv)
@@ -1728,6 +1744,10 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
		if (ap->flags & ATA_FLAG_EM)

			ap->em_message_type = hpriv->em_msg_type;



		if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&

		    mobile_lpm_policy >= ATA_LPM_UNKNOWN &&

		    mobile_lpm_policy <= ATA_LPM_MIN_POWER)

			ap->target_lpm_policy = mobile_lpm_policy;



		/* disabled/not-implemented port */

		if (!(hpriv->port_map & (1 << i)))

drivers/ata/ahci.h

+3 −0
Original line number Diff line number Diff line
@@ -251,6 +251,9 @@ enum { 
	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */

	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read

							only registers */

	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use

							SATA_MOBILE_LPM_POLICY

							as default lpm_policy */



	/* ap->flags bits */

drivers/ata/ahci_brcm.c

+102 −18
Original line number Diff line number Diff line
@@ -70,6 +70,13 @@ 
	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\

	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))



#define BUS_CTRL_ENDIAN_NSP_CONF			\

	(0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)



#define BUS_CTRL_ENDIAN_CONF_MASK			\

	(0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT |	\

	 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)



enum brcm_ahci_version {

	BRCM_SATA_BCM7425 = 1,

	BRCM_SATA_BCM7445,
@@ -89,14 +96,6 @@ struct brcm_ahci_priv { 
	enum brcm_ahci_version version;

};



static const struct ata_port_info ahci_brcm_port_info = {

	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,

	.link_flags	= ATA_LFLAG_NO_DB_DELAY,

	.pio_mask	= ATA_PIO4,

	.udma_mask	= ATA_UDMA6,

	.port_ops	= &ahci_platform_ops,

};



static inline u32 brcm_sata_readreg(void __iomem *addr)

{

	/*
@@ -250,20 +249,105 @@ static u32 brcm_ahci_get_portmask(struct platform_device *pdev, 
static void brcm_sata_init(struct brcm_ahci_priv *priv)

{

	void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;

	u32 data;



	/* Configure endianness */

	if (priv->version ==  BRCM_SATA_NSP) {

		u32 data = brcm_sata_readreg(ctrl);



		data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) |

			(0x03 << DMADESC_ENDIAN_SHIFT));

		data |= (0x02 << DMADATA_ENDIAN_SHIFT) |

			(0x02 << DMADESC_ENDIAN_SHIFT);

	data = brcm_sata_readreg(ctrl);

	data &= ~BUS_CTRL_ENDIAN_CONF_MASK;

	if (priv->version == BRCM_SATA_NSP)

		data |= BUS_CTRL_ENDIAN_NSP_CONF;

	else

		data |= BUS_CTRL_ENDIAN_CONF;

	brcm_sata_writereg(data, ctrl);

	} else

		brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);

}



static unsigned int brcm_ahci_read_id(struct ata_device *dev,

				      struct ata_taskfile *tf, u16 *id)

{

	struct ata_port *ap = dev->link->ap;

	struct ata_host *host = ap->host;

	struct ahci_host_priv *hpriv = host->private_data;

	struct brcm_ahci_priv *priv = hpriv->plat_data;

	void __iomem *mmio = hpriv->mmio;

	unsigned int err_mask;

	unsigned long flags;

	int i, rc;

	u32 ctl;



	/* Try to read the device ID and, if this fails, proceed with the

	 * recovery sequence below

	 */

	err_mask = ata_do_dev_read_id(dev, tf, id);

	if (likely(!err_mask))

		return err_mask;



	/* Disable host interrupts */

	spin_lock_irqsave(&host->lock, flags);

	ctl = readl(mmio + HOST_CTL);

	ctl &= ~HOST_IRQ_EN;

	writel(ctl, mmio + HOST_CTL);

	readl(mmio + HOST_CTL); /* flush */

	spin_unlock_irqrestore(&host->lock, flags);



	/* Perform the SATA PHY reset sequence */

	brcm_sata_phy_disable(priv, ap->port_no);



	/* Bring the PHY back on */

	brcm_sata_phy_enable(priv, ap->port_no);



	/* Re-initialize and calibrate the PHY */

	for (i = 0; i < hpriv->nports; i++) {

		rc = phy_init(hpriv->phys[i]);

		if (rc)

			goto disable_phys;



		rc = phy_calibrate(hpriv->phys[i]);

		if (rc) {

			phy_exit(hpriv->phys[i]);

			goto disable_phys;

		}

	}



	/* Re-enable host interrupts */

	spin_lock_irqsave(&host->lock, flags);

	ctl = readl(mmio + HOST_CTL);

	ctl |= HOST_IRQ_EN;

	writel(ctl, mmio + HOST_CTL);

	readl(mmio + HOST_CTL); /* flush */

	spin_unlock_irqrestore(&host->lock, flags);



	return ata_do_dev_read_id(dev, tf, id);



disable_phys:

	while (--i >= 0) {

		phy_power_off(hpriv->phys[i]);

		phy_exit(hpriv->phys[i]);

	}



	return AC_ERR_OTHER;

}



static void brcm_ahci_host_stop(struct ata_host *host)

{

	struct ahci_host_priv *hpriv = host->private_data;



	ahci_platform_disable_resources(hpriv);

}



static struct ata_port_operations ahci_brcm_platform_ops = {

	.inherits	= &ahci_ops,

	.host_stop	= brcm_ahci_host_stop,

	.read_id	= brcm_ahci_read_id,

};



static const struct ata_port_info ahci_brcm_port_info = {

	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,

	.link_flags	= ATA_LFLAG_NO_DB_DELAY,

	.pio_mask	= ATA_PIO4,

	.udma_mask	= ATA_UDMA6,

	.port_ops	= &ahci_brcm_platform_ops,

};



#ifdef CONFIG_PM_SLEEP

static int brcm_ahci_suspend(struct device *dev)

{