Loading drivers/clk/qcom/camcc-sm8150.c +15 −0 Original line number Diff line number Diff line Loading @@ -589,6 +589,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -609,6 +610,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -635,6 +637,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -661,6 +664,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -681,6 +685,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -701,6 +706,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -721,6 +727,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -751,6 +758,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -984,6 +992,7 @@ static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_0_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1030,6 +1039,7 @@ static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_1_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1184,6 +1194,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1204,6 +1215,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1224,6 +1236,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1244,6 +1257,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_1, Loading Loading @@ -1272,6 +1286,7 @@ static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_qdss_debug_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading
drivers/clk/qcom/camcc-sm8150.c +15 −0 Original line number Diff line number Diff line Loading @@ -589,6 +589,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -609,6 +610,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -635,6 +637,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -661,6 +664,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -681,6 +685,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -701,6 +706,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading @@ -721,6 +727,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -751,6 +758,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -984,6 +992,7 @@ static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_0_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1030,6 +1039,7 @@ static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_1_clk_src", .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1184,6 +1194,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1204,6 +1215,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1224,6 +1236,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_1, Loading @@ -1244,6 +1257,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_1, Loading Loading @@ -1272,6 +1286,7 @@ static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_qdss_debug_clk_src", .parent_names = cam_cc_parent_names_0, Loading
