iommu/arm-smmu: Merge of iommu changes from msm-4.9 into msm-next

                        "arm,mmu-401"

                        "arm,mmu-401"

                        "arm,mmu-500"

                        "arm,mmu-500"

                        "cavium,smmu-v2"

                        "cavium,smmu-v2"

                        "qcom,smmu-v2"

                        "qcom,qsmmu-v500"

                  depending on the particular implementation and/or the

                  depending on the particular implementation and/or the

                  version of the architecture implemented.

                  version of the architecture implemented.

- reg           : Base address and size of the SMMU.

- reg           : Base address and size of the SMMU.

- reg-names	: For the "qcom,qsmmu-v500" device "tcu-base" is expected.

- #global-interrupts : The number of global interrupts exposed by the

- #global-interrupts : The number of global interrupts exposed by the

                       device.

                       device.

                  combined interrupt, it must be listed multiple times.

                  combined interrupt, it must be listed multiple times.

- #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt

- #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt

                  for details. With a value of 1, each IOMMU specifier

                  for details. With a value of 1, each "iommus" entry

                  represents a distinct stream ID emitted by that device

                  represents a distinct stream ID emitted by that device

                  into the relevant SMMU.

                  into the relevant SMMU.

                  SMMUs with stream matching support and complex masters

                  SMMUs with stream matching support and complex masters

                  may use a value of 2, where the second cell of the

                  may use a value of 2, where the second cell represents

                  IOMMU specifier represents an SMR mask to combine with

                  an SMR mask to combine with the ID in the first cell.

                  the ID in the first cell.  Care must be taken to ensure

                  Care must be taken to ensure the set of matched IDs

                  the set of matched IDs does not result in conflicts.

                  does not result in conflicts.

** System MMU optional properties:

** System MMU optional properties:

                  aliases of secure registers have to be used during

                  aliases of secure registers have to be used during

                  SMMU configuration.

                  SMMU configuration.

- stream-match-mask : For SMMUs supporting stream matching and using

- attach-impl-defs : global registers to program at device attach

                  #iommu-cells = <1>, specifies a mask of bits to ignore

                  time. This should be a list of 2-tuples of the format:

		  when matching stream IDs (e.g. this may be programmed

                  <offset reg_value>.

		  into the SMRn.MASK field of every stream match register

		  used). For cases where it is desirable to ignore some

- qcom,fatal-asf : Enable BUG_ON for address size faults.  Some hardware

                  portion of every Stream ID (e.g. for certain MMU-500

                  requires special fixups to recover from address size

                  configurations given globally unique input IDs). This

                  faults.  Rather than applying the fixups just BUG since

                  property is not valid for SMMUs using stream indexing,

                  address size faults are due to a fundamental programming

                  or using stream matching with #iommu-cells = <2>, and

                  error from which we don't care about recovering anyways.

                  may be ignored if present in such cases.

- qcom,skip-init : Disable resetting configuration for all context banks

                  during device reset.  This is useful for targets where

                  some context banks are dedicated to other execution

                  environments outside of Linux and those other EEs are

                  programming their own stream match tables, SCTLR, etc.

                  Without setting this option we will trample on their

                  configuration.

- qcom,dynamic  : Allow dynamic domains to be attached. This is only

		  useful if the upstream hardware is capable of switching

		  between multiple domains within a single context bank.

- qcom,use-3-lvl-tables:

		  Some hardware configurations may not be optimized for using

		  a four level page table configuration. Set to use a three

		  level page table instead.

- qcom,no-asid-retention:

		  Some hardware may lose internal state for asid after

		  retention. No cache invalidation operations involving asid

		  may be used.

- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified

                  here, there must be a corresponding entry in clock-names

                  (see below).

- clock-names   : List of clock names corresponding to the clocks specified in

                  the "clocks" property (above). See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for more info.

- (%s)-supply   : Phandle of the regulator that should be powered on during

                  SMMU register access. (%s) is a string from the

		  qcom,regulator-names property.

- qcom,regulator-names :

		  List of strings to use with the (%s)-supply property.

- qcom,msm-bus,name

- qcom,msm-bus,num-cases

- qcom,msm-bus,num-paths

- qcom,msm-bus,vectors-KBps

		: Refer to devicetree/bindings/arm/msm/msm_bus.txt

** Deprecated properties:

** Deprecated properties:

        };

        };

        /* ARM MMU-500 with 10-bit stream ID input configuration */

* Qualcomm MMU-500 TBU Device

        smmu3: iommu {

                compatible = "arm,mmu-500", "arm,smmu-v2";

                ...

                #iommu-cells = <1>;

                /* always ignore appended 5-bit TBU number */

                stream-match-mask = 0x7c00;

        };

        bus {

The qcom,qsmmu-v500 device implements a number of register regions containing

                /* bus whose child devices emit one unique 10-bit stream

debug functionality. Each register region maps to a separate tbu from the

                   ID each, but may master through multiple SMMU TBUs */

arm mmu-500 implementation.

                iommu-map = <0 &smmu3 0 0x400>;

                ...

** TBU required properties:

- compatible    : Should be one of:

                        "qcom,qsmmuv500-tbu"

- reg           : Base address and size.

- reg-names	: "base" and "status-reg" are expected

		"base" is the main TBU register region.

		"status-reg" indicates whether hw can process a new request.

-qcom,stream-id-range:

		Pair of values describing the smallest supported stream-id

		and the size of the entire set.

Example:

smmu {

	compatible = "qcom,qsmmu-v500";

	tbu@0x1000 {

		compatible = "qcom,qsmmuv500-tbu";

		regs = <0x1000 0x1000>,

			<0x2000 0x8>;

		reg-names = "base",

			"status-reg";

		qcom,stream-id-range = <0x800 0x400>;

	};

};

};

This document describes the device tree binding for IOMMU test devices.

The iommu-debug framework can optionally make use of some platform devices

for improved standalone testing and other features.

- compatible: iommu-debug-test

Required properties

===================

- iommus: The IOMMU for the test device (see iommu.txt)

Example

=======

	iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * 42 shouldn't be used by anyone on the cpp_fd_smmu.  We just

		 * need _something_ here to get this node recognized by the

		 * SMMU driver. Our test uses ATOS, which doesn't use SIDs

		 * anyways, so using a dummy value is ok.

		 */

		iommus = <&cpp_fd_smmu 42>;

	};

source "mm/Kconfig"

source "mm/Kconfig"

config ARM64_DMA_USE_IOMMU

	bool "ARM64 DMA iommu integration"

	select ARM_HAS_SG_CHAIN

	select NEED_SG_DMA_LENGTH

	help

	  Enable using iommu through the standard dma apis.

	  dma_alloc_coherent() will allocate scatter-gather memory

	  which is made virtually contiguous via iommu.

	  Enable if system contains IOMMU hardware.

if ARM64_DMA_USE_IOMMU

config ARM64_DMA_IOMMU_ALIGNMENT

	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"

	range 4 9

	default 9

	help

	  DMA mapping framework by default aligns all buffers to the smallest

	  PAGE_SIZE order which is greater than or equal to the requested buffer

	  size. This works well for buffers up to a few hundreds kilobytes, but

	  for larger buffers it just a waste of address space. Drivers which has

	  relatively small addressing window (like 64Mib) might run out of

	  virtual space with just a few allocations.

	  With this parameter you can specify the maximum PAGE_SIZE order for

	  DMA IOMMU buffers. Larger buffers will be aligned only to this

	  specified order. The order is expressed as a power of two multiplied

	  by the PAGE_SIZE.

endif

config SECCOMP

config SECCOMP

	bool "Enable seccomp to safely compute untrusted bytecode"

	bool "Enable seccomp to safely compute untrusted bytecode"

	---help---

	---help---

/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/msm/msm-bus-ids.h>

&soc {

	kgsl_smmu: kgsl-smmu@0x02CA0000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x02CA0000 0x10000>,

			<0x2CC2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <1>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,no-asid-retention;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;

		gfx_0_tbu: gfx_0_tbu@0x2CC5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x2CC5000 0x1000>,

				<0x2CC2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};

		gfx_1_tbu: gfx_1_tbu@0x2CC9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x2CC9000 0x1000>,

				<0x2CC2208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

	};

	apps_smmu: apps-smmu@0x15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x100000>,

			<0x15182000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,no-asid-retention;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;

		anoc_1_tbu: anoc_1_tbu@0x15185000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15185000 0x1000>,

				<0x15182200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};

		anoc_2_tbu: anoc_2_tbu@0x15189000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15189000 0x1000>,

				<0x15182208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1518D000 0x1000>,

				<0x15182210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

		};

		mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15191000 0x1000>,

				<0x15182218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

		};

		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15195000 0x1000>,

				<0x15182220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

		};

		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15199000 0x1000>,

				<0x15182228 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

		};

		adsp_tbu: adsp_tbu@0x1519D000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x1519D000 0x1000>,

				<0x15182230 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1800 0x400>;

		};

		anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151A1000 0x1000>,

				<0x15182238 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1c00 0x400>;

		};

		compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x151A5000 0x1000>,

				<0x15182240 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1c00 0x400>;

		};

	};

	kgsl_iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * 0x7 isn't a valid sid, but should pass the sid sanity check.

		 * We just need _something_ here to get this node recognized by

		 * the SMMU driver. Our test uses ATOS, which doesn't use SIDs

		 * anyways, so using a dummy value is ok.

		 */

		iommus = <&kgsl_smmu 0x7>;

	};

	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * This SID belongs to TSIF. We can't use a fake SID for

		 * the apps_smmu device.

		 */

		iommus = <&apps_smmu 0x20 0>;

	};

};

#include "sdm855-regulator.dtsi"

#include "sdm855-regulator.dtsi"

#include "sdm855-ion.dtsi"

#include "sdm855-ion.dtsi"

#include "sdm855-smp2p.dtsi"

#include "sdm855-smp2p.dtsi"

#include "msm-arm-smmu-sdm855.dtsi"