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Commit 72021788 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Eric Anholt
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drm/i915: add support for G41 chipset 



This had been delayed for some time due to failure to work on the one piece
of G41 hardware we had, and lack of success reports from anybody else.
Current hardware appears to be OK.

Signed-off-by: default avatarZhenyu Wang <zhenyu.z.wang@intel.com>
[anholt: hand-applied due to conflicts with IGD patches]
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 44ab4315

drivers/gpu/drm/i915/i915_drv.h

+3 −1
Original line number Original line Diff line number Diff line
@@ -787,7 +787,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
		       (dev)->pci_device == 0x2A42 || \

		       (dev)->pci_device == 0x2A42 || \

		       (dev)->pci_device == 0x2E02 || \

		       (dev)->pci_device == 0x2E02 || \

		       (dev)->pci_device == 0x2E12 || \

		       (dev)->pci_device == 0x2E12 || \

		       (dev)->pci_device == 0x2E22)

		       (dev)->pci_device == 0x2E22 || \

		       (dev)->pci_device == 0x2E32)





#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
@@ -796,6 +797,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \

#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \

		     (dev)->pci_device == 0x2E12 || \

		     (dev)->pci_device == 0x2E12 || \

		     (dev)->pci_device == 0x2E22 || \

		     (dev)->pci_device == 0x2E22 || \

		     (dev)->pci_device == 0x2E32 || \

		     IS_GM45(dev))

		     IS_GM45(dev))





#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)

#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)

include/drm/drm_pciids.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -532,6 +532,7 @@ 
	{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x2e32, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \

	{0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \