Merge "UPSTREAM: ath10k: snoc: sort include files" (712c6458) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/net/wireless/ath/ath10k/ce.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -620,7 +620,7 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries)
		/* Prevent CE ring stuck issue that will occur when ring is full.
		* Make sure that write index is 1 less than read index.
		*/
		if ((cur_write_idx + nentries) == dest_ring->sw_index)
		if (((cur_write_idx + nentries) & nentries_mask) == dest_ring->sw_index)
		nentries -= 1;

		write_index = CE_RING_IDX_ADD(nentries_mask, write_index, nentries);

drivers/net/wireless/ath/ath10k/ce.h

+49 −3

Original line number	Diff line number	Diff line
		@@ -354,14 +354,60 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
		(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
		#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
		#define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0))

		static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
		{
		struct ath10k_ce *ce = ath10k_ce_priv(ar);

		if (!ar->hw_params.per_ce_irq)
		return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
		ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
		else
		return CE_INTERRUPT_SUMMARY;
		}

		/* Host software's Copy Engine configuration. */
		#define CE_ATTR_FLAGS 0

		/*
		* Configuration information for a Copy Engine pipe.
		* Passed from Host to Target during startup (one per CE).
		*
		* NOTE: Structure is shared between Host software and Target firmware!
		*/
		struct ce_pipe_config {
		__le32 pipenum;
		__le32 pipedir;
		__le32 nentries;
		__le32 nbytes_max;
		__le32 flags;
		__le32 reserved;
		};

		/*
		* Directions for interconnect pipe configuration.
		* These definitions may be used during configuration and are shared
		* between Host and Target.
		*
		* Pipe Directions are relative to the Host, so PIPEDIR_IN means
		* "coming IN over air through Target to Host" as with a WiFi Rx operation.
		* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
		* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
		* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
		* over the interconnect.
		*/
		#define PIPEDIR_NONE 0
		#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
		#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
		#define PIPEDIR_INOUT 3 /* bidirectional */

		/* Establish a mapping between a service/direction and a pipe. */
		struct service_to_pipe {
		__le32 service_id;
		__le32 pipedir;
		__le32 pipenum;
		};

		#endif /* _CE_H_ */

drivers/net/wireless/ath/ath10k/core.c

+21 −0

Original line number	Diff line number	Diff line
		@@ -89,6 +89,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA9887_HW_1_0_VERSION,
		@@ -118,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA6174_HW_2_1_VERSION,
		@@ -146,6 +148,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA6174_HW_2_1_VERSION,
		@@ -174,6 +177,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA6174_HW_3_0_VERSION,
		@@ -202,6 +206,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA6174_HW_3_2_VERSION,
		@@ -233,6 +238,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA99X0_HW_2_0_DEV_VERSION,
		@@ -267,6 +273,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA9984_HW_1_0_DEV_VERSION,
		@@ -306,6 +313,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA9888_HW_2_0_DEV_VERSION,
		@@ -344,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA9377_HW_1_0_DEV_VERSION,
		@@ -372,6 +381,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA9377_HW_1_1_DEV_VERSION,
		@@ -402,6 +412,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = QCA4019_HW_1_0_DEV_VERSION,
		@@ -437,6 +448,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = 0x20,
		.target_64bit = false,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
		.per_ce_irq = false,
		},
		{
		.id = WCN3990_HW_1_0_DEV_VERSION,
		@@ -457,6 +469,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
		.target_64bit = true,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
		.per_ce_irq = true,
		},
		};

		@@ -2437,6 +2450,14 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
		ar->hw->wiphy->hw_version = target_info.version;
		break;
		case ATH10K_BUS_SNOC:
		memset(&target_info, 0, sizeof(target_info));
		ret = ath10k_hif_get_target_info(ar, &target_info);
		if (ret) {
		ath10k_err(ar, "could not get target info (%d)\n", ret);
		goto err_power_down;
		}
		ar->target_version = target_info.version;
		ar->hw->wiphy->hw_version = target_info.version;
		break;
		default:
		ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);

drivers/net/wireless/ath/ath10k/hif.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@

		#include <linux/kernel.h>
		#include "core.h"
		#include "bmi.h"
		#include "debug.h"

		struct ath10k_hif_sg_item {
		@@ -93,6 +94,9 @@ struct ath10k_hif_ops {
		/* fetch calibration data from target eeprom */
		int (fetch_cal_eeprom)(struct ath10k ar, void **data,
		size_t *data_len);

		int (get_target_info)(struct ath10k ar,
		struct bmi_target_info *target_info);
		};

		static inline int ath10k_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
		@@ -218,4 +222,13 @@ static inline int ath10k_hif_fetch_cal_eeprom(struct ath10k *ar,
		return ar->hif.ops->fetch_cal_eeprom(ar, data, data_len);
		}

		static inline int ath10k_hif_get_target_info(struct ath10k *ar,
		struct bmi_target_info *tgt_info)
		{
		if (!ar->hif.ops->get_target_info)
		return -EOPNOTSUPP;

		return ar->hif.ops->get_target_info(ar, tgt_info);
		}

		#endif /* _HIF_H_ */

drivers/net/wireless/ath/ath10k/htt.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -127,6 +127,19 @@ struct htt_msdu_ext_desc_64 {
		\| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
		\| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)

		#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16)
		#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17)
		#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18)
		#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19)
		#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20)
		#define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21)

		#define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \
		\| HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \
		\| HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \
		\| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \
		\| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64)

		enum htt_data_tx_desc_flags0 {
		HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
		HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,