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Commit 70883035 authored by Govinda Rajulu Chenna's avatar Govinda Rajulu Chenna Committed by Gerrit - the friendly Code Review server
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drm/msm/dp: add DP MST register definitions 



add DP MST link, channel allocation, ACT signalling,
stream timing engine configuration related register
definitions required for DP MST implementation.

CRs-Fixed: 2192818
Change-Id: I624ad62f626a4c0aa1436a58b920d194fa22fd81
Signed-off-by: default avatarGovinda Rajulu Chenna <gchenna@codeaurora.org>
parent 6c2c26ad

drivers/gpu/drm/msm/dp/dp_reg.h

+72 −0
Original line number Diff line number Diff line
@@ -58,6 +58,24 @@ 
#define DP_VALID_BOUNDARY_2			(0x00000034)

#define DP_LOGICAL2PHYSICAL_LANE_MAPPING	(0x00000038)



#define DP1_CONFIGURATION_CTRL			(0x00000400)

#define DP_DP0_TIMESLOT_1_32			(0x00000404)

#define DP_DP0_TIMESLOT_33_63			(0x00000408)

#define DP_DP1_TIMESLOT_1_32			(0x0000040C)

#define DP_DP1_TIMESLOT_33_63			(0x00000410)

#define DP1_SOFTWARE_MVID			(0x00000414)

#define DP1_SOFTWARE_NVID			(0x00000418)

#define DP1_TOTAL_HOR_VER			(0x0000041C)

#define DP1_START_HOR_VER_FROM_SYNC		(0x00000420)

#define DP1_HSYNC_VSYNC_WIDTH_POLARITY		(0x00000424)

#define DP1_ACTIVE_HOR_VER			(0x00000428)

#define DP1_MISC1_MISC0				(0x0000042C)

#define DP_DP0_RG				(0x000004F8)

#define DP_DP1_RG				(0x000004FC)



#define DP_MST_ACT				(0x00000500)

#define DP_MST_MAINLINK_READY			(0x00000504)



#define DP_MAINLINK_READY			(0x00000040)

#define DP_MAINLINK_LEVELS			(0x00000044)

#define DP_TU					(0x0000004C)
@@ -123,6 +141,8 @@ 
#define MMSS_DP_AUDIO_INFOFRAME_1		(0x000002AC)

#define MMSS_DP_AUDIO_INFOFRAME_2		(0x000002B0)



#define MMSS_DP_FLUSH				(0x000002F8)



#define MMSS_DP_GENERIC0_0			(0x00000300)

#define MMSS_DP_GENERIC0_1			(0x00000304)

#define MMSS_DP_GENERIC0_2			(0x00000308)
@@ -144,6 +164,31 @@ 
#define MMSS_DP_GENERIC1_8			(0x00000348)

#define MMSS_DP_GENERIC1_9			(0x0000034C)



#define MMSS_DP1_GENERIC0_0			(0x00000490)

#define MMSS_DP1_GENERIC0_1			(0x00000494)

#define MMSS_DP1_GENERIC0_2			(0x00000498)

#define MMSS_DP1_GENERIC0_3			(0x0000049C)

#define MMSS_DP1_GENERIC0_4			(0x000004A0)

#define MMSS_DP1_GENERIC0_5			(0x000004A4)

#define MMSS_DP1_GENERIC0_6			(0x000004A8)

#define MMSS_DP1_GENERIC0_7			(0x000004AC)

#define MMSS_DP1_GENERIC0_8			(0x000004B0)

#define MMSS_DP1_GENERIC0_9			(0x000004B4)

#define MMSS_DP1_GENERIC1_0			(0x000004B8)

#define MMSS_DP1_GENERIC1_1			(0x000004BC)

#define MMSS_DP1_GENERIC1_2			(0x000004C0)

#define MMSS_DP1_GENERIC1_3			(0x000004C4)

#define MMSS_DP1_GENERIC1_4			(0x000004C8)

#define MMSS_DP1_GENERIC1_5			(0x000004CC)

#define MMSS_DP1_GENERIC1_6			(0x000004D0)

#define MMSS_DP1_GENERIC1_7			(0x000004D4)

#define MMSS_DP1_GENERIC1_8			(0x000004D8)

#define MMSS_DP1_GENERIC1_9			(0x000004DC)



#define MMSS_DP1_SDP_CFG			(0x000004E0)

#define MMSS_DP1_SDP_CFG2			(0x000004E4)

#define MMSS_DP1_SDP_CFG3			(0x000004E8)



#define MMSS_DP_VSCEXT_0			(0x000002D0)

#define MMSS_DP_VSCEXT_1			(0x000002D4)

#define MMSS_DP_VSCEXT_2			(0x000002D8)
@@ -178,6 +223,29 @@ 
#define MMSS_DP_TPG_VIDEO_CONFIG		(0x00000064)

#define MMSS_DP_ASYNC_FIFO_CONFIG		(0x00000088)



#define MMSS_DP1_BIST_ENABLE			(0x00000000)

#define MMSS_DP1_TIMING_ENGINE_EN		(0x00000010)

#define MMSS_DP1_INTF_CONFIG			(0x00000014)

#define MMSS_DP1_INTF_HSYNC_CTL			(0x00000018)

#define MMSS_DP1_INTF_VSYNC_PERIOD_F0		(0x0000001C)

#define MMSS_DP1_INTF_VSYNC_PERIOD_F1		(0x00000020)

#define MMSS_DP1_INTF_VSYNC_PULSE_WIDTH_F0	(0x00000024)

#define MMSS_DP1_INTF_VSYNC_PULSE_WIDTH_F1	(0x00000028)

#define MMSS_DP1_INTF_DISPLAY_V_START_F0	(0x0000002C)

#define MMSS_DP1_INTF_DISPLAY_V_START_F1	(0x00000030)

#define MMSS_DP1_INTF_DISPLAY_V_END_F0		(0x00000034)

#define MMSS_DP1_INTF_DISPLAY_V_END_F1		(0x00000038)

#define MMSS_DP1_INTF_ACTIVE_V_START_F0		(0x0000003C)

#define MMSS_DP1_INTF_ACTIVE_V_START_F1		(0x00000040)

#define MMSS_DP1_INTF_ACTIVE_V_END_F0		(0x00000044)

#define MMSS_DP1_INTF_ACTIVE_V_END_F1		(0x00000048)

#define MMSS_DP1_INTF_DISPLAY_HCTL		(0x0000004C)

#define MMSS_DP1_INTF_ACTIVE_HCTL		(0x00000050)

#define MMSS_DP1_INTF_POLARITY_CTL		(0x00000058)

#define MMSS_DP1_TPG_MAIN_CONTROL		(0x00000060)

#define MMSS_DP1_TPG_VIDEO_CONFIG		(0x00000064)

#define MMSS_DP1_ASYNC_FIFO_CONFIG		(0x00000088)



/*DP PHY Register offsets */

#define DP_PHY_REVISION_ID0                     (0x00000000)

#define DP_PHY_REVISION_ID1                     (0x00000004)
@@ -220,6 +288,10 @@ 
#define MMSS_DP_PIXEL_N				(0x0178)

#define MMSS_DP_PIXEL_M_V420			(0x01B4)

#define MMSS_DP_PIXEL_N_V420			(0x01B8)

#define MMSS_DP_PIXEL1_M			(0x018C)

#define MMSS_DP_PIXEL1_N			(0x0190)

#define MMSS_DP_PIXEL1_M_V420			(0x01CC)

#define MMSS_DP_PIXEL1_N_V420			(0x01D0)



/* DP HDCP 1.3 registers */

#define DP_HDCP_CTRL                                   (0x0A0)