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Commit 70768496 authored by Sujith's avatar Sujith Committed by John W. Linville
Browse files

ath9k: Program the RTC registers correctly 



This patch programs the RTC registers of AR9100 chipsets
correctly during chip reset.

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 362695e1

drivers/net/wireless/ath9k/hw.c

+8 −0
Original line number Diff line number Diff line
@@ -1482,6 +1482,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 
	u32 rst_flags;

	u32 tmpReg;



	if (AR_SREV_9100(ah)) {

		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);

		val &= ~AR_RTC_DERIVED_CLK_PERIOD;

		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);

		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);

		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);

	}



	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |

		  AR_RTC_FORCE_WAKE_ON_INT);

drivers/net/wireless/ath9k/reg.h

+6 −2
Original line number Diff line number Diff line
@@ -977,8 +977,6 @@ enum { 
#define AR_RTC_PLL_CLKSEL       0x00000300

#define AR_RTC_PLL_CLKSEL_S     8







#define AR_RTC_RESET \

	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)

#define AR_RTC_RESET_EN		(0x00000001)
@@ -1015,6 +1013,12 @@ enum { 
#define AR_RTC_INTR_MASK \

	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)



/* RTC_DERIVED_* - only for AR9100 */



#define AR_RTC_DERIVED_CLK           (AR_RTC_BASE + 0x0038)

#define AR_RTC_DERIVED_CLK_PERIOD    0x0000fffe

#define AR_RTC_DERIVED_CLK_PERIOD_S  1



#define	AR_SEQ_MASK	0x8060



#define AR_AN_RF2G1_CH0         0x7810