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Commit 6ff4fd05 authored by ling.ma@intel.com's avatar ling.ma@intel.com Committed by Eric Anholt
Browse files

drm/i915: Set SSC frequency for 8xx chips correctly 



All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: default avatarMa Ling <ling.ma@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 7662c8bd

drivers/gpu/drm/i915/intel_bios.c

+6 −4
Original line number Diff line number Diff line
@@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv, 
		dev_priv->lvds_use_ssc = general->enable_ssc;



		if (dev_priv->lvds_use_ssc) {

		  if (IS_I855(dev_priv->dev))

		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;

			if (IS_I85X(dev_priv->dev))

				dev_priv->lvds_ssc_freq =

					general->ssc_freq ? 66 : 48;

			else

		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;

				dev_priv->lvds_ssc_freq =

					general->ssc_freq ? 100 : 96;

		}

	}

}