Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6de20451 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: Add printing of ES bit for Imgtec cores when cache error occurs. 



The cacheer register is always implemented in the same way in the
MIPS32r2 Imgtec cores so print the ES bit when an cache error
occurs.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6041/
parent 5cf8b240

arch/mips/kernel/traps.c

+21 −8
Original line number Diff line number Diff line
@@ -1425,14 +1425,27 @@ asmlinkage void cache_parity_error(void) 
	printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",

	       reg_val & (1<<30) ? "secondary" : "primary",

	       reg_val & (1<<31) ? "data" : "insn");

	printk("Error bits: %s%s%s%s%s%s%s\n",

	if (cpu_has_mips_r2 &&

	    ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {

		pr_err("Error bits: %s%s%s%s%s%s%s%s\n",

			reg_val & (1<<29) ? "ED " : "",

			reg_val & (1<<28) ? "ET " : "",

			reg_val & (1<<27) ? "ES " : "",

			reg_val & (1<<26) ? "EE " : "",

			reg_val & (1<<25) ? "EB " : "",

			reg_val & (1<<24) ? "EI " : "",

			reg_val & (1<<23) ? "E1 " : "",

			reg_val & (1<<22) ? "E0 " : "");

	} else {

		pr_err("Error bits: %s%s%s%s%s%s%s\n",

			reg_val & (1<<29) ? "ED " : "",

			reg_val & (1<<28) ? "ET " : "",

			reg_val & (1<<26) ? "EE " : "",

			reg_val & (1<<25) ? "EB " : "",

			reg_val & (1<<24) ? "EI " : "",

			reg_val & (1<<23) ? "E1 " : "",

			reg_val & (1<<22) ? "E0 " : "");

	}

	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));



#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)