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Commit 6d7c2b4c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon/kms: Make GPU/CPU page size handling consistent in blit code (v2)
  drm/radeon/kms: fix typo in r100_blit_copy
  drm/radeon: Unreference GEM object outside of spinlock in page flip error path.
  drm/radeon: Don't read from CP ring write pointer registers.
  drm/ttm: request zeroed system memory pages for new TT buffer objects
parents 1f0772fe 003cefe0

drivers/gpu/drm/radeon/evergreen.c

+8 −6
Original line number Original line Diff line number Diff line
@@ -1404,7 +1404,8 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
	/* Initialize the ring buffer's read and write pointers */

	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_RPTR_WR, 0);

	WREG32(CP_RB_RPTR_WR, 0);

	WREG32(CP_RB_WPTR, 0);

	rdev->cp.wptr = 0;

	WREG32(CP_RB_WPTR, rdev->cp.wptr);





	/* set the wb address wether it's enabled or not */

	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB_RPTR_ADDR,

	WREG32(CP_RB_RPTR_ADDR,
@@ -1426,7 +1427,6 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));

	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));





	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	rdev->cp.wptr = RREG32(CP_RB_WPTR);





	evergreen_cp_start(rdev);

	evergreen_cp_start(rdev);

	rdev->cp.ready = true;

	rdev->cp.ready = true;
@@ -3171,21 +3171,23 @@ int evergreen_suspend(struct radeon_device *rdev) 
}

}





int evergreen_copy_blit(struct radeon_device *rdev,

int evergreen_copy_blit(struct radeon_device *rdev,

			uint64_t src_offset, uint64_t dst_offset,

			uint64_t src_offset,

			unsigned num_pages, struct radeon_fence *fence)

			uint64_t dst_offset,

			unsigned num_gpu_pages,

			struct radeon_fence *fence)

{

{

	int r;

	int r;





	mutex_lock(&rdev->r600_blit.mutex);

	mutex_lock(&rdev->r600_blit.mutex);

	rdev->r600_blit.vb_ib = NULL;

	rdev->r600_blit.vb_ib = NULL;

	r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);

	r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);

	if (r) {

	if (r) {

		if (rdev->r600_blit.vb_ib)

		if (rdev->r600_blit.vb_ib)

			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

		mutex_unlock(&rdev->r600_blit.mutex);

		mutex_unlock(&rdev->r600_blit.mutex);

		return r;

		return r;

	}

	}

	evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);

	evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);

	evergreen_blit_done_copy(rdev, fence);

	evergreen_blit_done_copy(rdev, fence);

	mutex_unlock(&rdev->r600_blit.mutex);

	mutex_unlock(&rdev->r600_blit.mutex);

	return 0;

	return 0;

drivers/gpu/drm/radeon/ni.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -1187,7 +1187,8 @@ int cayman_cp_resume(struct radeon_device *rdev) 




	/* Initialize the ring buffer's read and write pointers */

	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB0_WPTR, 0);

	rdev->cp.wptr = 0;

	WREG32(CP_RB0_WPTR, rdev->cp.wptr);





	/* set the wb address wether it's enabled or not */

	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1207,7 +1208,6 @@ int cayman_cp_resume(struct radeon_device *rdev) 
	WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);

	WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);





	rdev->cp.rptr = RREG32(CP_RB0_RPTR);

	rdev->cp.rptr = RREG32(CP_RB0_RPTR);

	rdev->cp.wptr = RREG32(CP_RB0_WPTR);





	/* ring1  - compute only */

	/* ring1  - compute only */

	/* Set ring buffer size */

	/* Set ring buffer size */
@@ -1220,7 +1220,8 @@ int cayman_cp_resume(struct radeon_device *rdev) 




	/* Initialize the ring buffer's read and write pointers */

	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB1_WPTR, 0);

	rdev->cp1.wptr = 0;

	WREG32(CP_RB1_WPTR, rdev->cp1.wptr);





	/* set the wb address wether it's enabled or not */

	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1232,7 +1233,6 @@ int cayman_cp_resume(struct radeon_device *rdev) 
	WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);

	WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);





	rdev->cp1.rptr = RREG32(CP_RB1_RPTR);

	rdev->cp1.rptr = RREG32(CP_RB1_RPTR);

	rdev->cp1.wptr = RREG32(CP_RB1_WPTR);





	/* ring2 - compute only */

	/* ring2 - compute only */

	/* Set ring buffer size */

	/* Set ring buffer size */
@@ -1245,7 +1245,8 @@ int cayman_cp_resume(struct radeon_device *rdev) 




	/* Initialize the ring buffer's read and write pointers */

	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB2_WPTR, 0);

	rdev->cp2.wptr = 0;

	WREG32(CP_RB2_WPTR, rdev->cp2.wptr);





	/* set the wb address wether it's enabled or not */

	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);

	WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1257,7 +1258,6 @@ int cayman_cp_resume(struct radeon_device *rdev) 
	WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);

	WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);





	rdev->cp2.rptr = RREG32(CP_RB2_RPTR);

	rdev->cp2.rptr = RREG32(CP_RB2_RPTR);

	rdev->cp2.wptr = RREG32(CP_RB2_WPTR);





	/* start the rings */

	/* start the rings */

	cayman_cp_start(rdev);

	cayman_cp_start(rdev);

drivers/gpu/drm/radeon/r100.c

+10 −12
Original line number Original line Diff line number Diff line
@@ -721,11 +721,11 @@ void r100_fence_ring_emit(struct radeon_device *rdev, 
int r100_copy_blit(struct radeon_device *rdev,

int r100_copy_blit(struct radeon_device *rdev,

		   uint64_t src_offset,

		   uint64_t src_offset,

		   uint64_t dst_offset,

		   uint64_t dst_offset,

		   unsigned num_pages,

		   unsigned num_gpu_pages,

		   struct radeon_fence *fence)

		   struct radeon_fence *fence)

{

{

	uint32_t cur_pages;

	uint32_t cur_pages;

	uint32_t stride_bytes = PAGE_SIZE;

	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;

	uint32_t pitch;

	uint32_t pitch;

	uint32_t stride_pixels;

	uint32_t stride_pixels;

	unsigned ndw;

	unsigned ndw;
@@ -737,7 +737,7 @@ int r100_copy_blit(struct radeon_device *rdev, 
	/* radeon pitch is /64 */

	/* radeon pitch is /64 */

	pitch = stride_bytes / 64;

	pitch = stride_bytes / 64;

	stride_pixels = stride_bytes / 4;

	stride_pixels = stride_bytes / 4;

	num_loops = DIV_ROUND_UP(num_pages, 8191);

	num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);





	/* Ask for enough room for blit + flush + fence */

	/* Ask for enough room for blit + flush + fence */

	ndw = 64 + (10 * num_loops);

	ndw = 64 + (10 * num_loops);
@@ -746,12 +746,12 @@ int r100_copy_blit(struct radeon_device *rdev, 
		DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);

		DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);

		return -EINVAL;

		return -EINVAL;

	}

	}

	while (num_pages > 0) {

	while (num_gpu_pages > 0) {

		cur_pages = num_pages;

		cur_pages = num_gpu_pages;

		if (cur_pages > 8191) {

		if (cur_pages > 8191) {

			cur_pages = 8191;

			cur_pages = 8191;

		}

		}

		num_pages -= cur_pages;

		num_gpu_pages -= cur_pages;





		/* pages are in Y direction - height

		/* pages are in Y direction - height

		   page width in X direction - width */

		   page width in X direction - width */
@@ -773,8 +773,8 @@ int r100_copy_blit(struct radeon_device *rdev, 
		radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));

		radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));

		radeon_ring_write(rdev, 0);

		radeon_ring_write(rdev, 0);

		radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));

		radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));

		radeon_ring_write(rdev, num_pages);

		radeon_ring_write(rdev, cur_pages);

		radeon_ring_write(rdev, num_pages);

		radeon_ring_write(rdev, cur_pages);

		radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));

		radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));

	}

	}

	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));

	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
@@ -990,7 +990,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	/* Force read & write ptr to 0 */

	/* Force read & write ptr to 0 */

	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);

	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);

	WREG32(RADEON_CP_RB_RPTR_WR, 0);

	WREG32(RADEON_CP_RB_RPTR_WR, 0);

	WREG32(RADEON_CP_RB_WPTR, 0);

	rdev->cp.wptr = 0;

	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);





	/* set the wb address whether it's enabled or not */

	/* set the wb address whether it's enabled or not */

	WREG32(R_00070C_CP_RB_RPTR_ADDR,

	WREG32(R_00070C_CP_RB_RPTR_ADDR,
@@ -1007,9 +1008,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	WREG32(RADEON_CP_RB_CNTL, tmp);

	WREG32(RADEON_CP_RB_CNTL, tmp);

	udelay(10);

	udelay(10);

	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);

	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);

	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);

	/* protect against crazy HW on resume */

	rdev->cp.wptr &= rdev->cp.ptr_mask;

	/* Set cp mode to bus mastering & enable cp*/

	/* Set cp mode to bus mastering & enable cp*/

	WREG32(RADEON_CP_CSQ_MODE,

	WREG32(RADEON_CP_CSQ_MODE,

	       REG_SET(RADEON_INDIRECT2_START, indirect2_start) |

	       REG_SET(RADEON_INDIRECT2_START, indirect2_start) |

drivers/gpu/drm/radeon/r200.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -84,7 +84,7 @@ static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) 
int r200_copy_dma(struct radeon_device *rdev,

int r200_copy_dma(struct radeon_device *rdev,

		  uint64_t src_offset,

		  uint64_t src_offset,

		  uint64_t dst_offset,

		  uint64_t dst_offset,

		  unsigned num_pages,

		  unsigned num_gpu_pages,

		  struct radeon_fence *fence)

		  struct radeon_fence *fence)

{

{

	uint32_t size;

	uint32_t size;
@@ -93,7 +93,7 @@ int r200_copy_dma(struct radeon_device *rdev, 
	int r = 0;

	int r = 0;





	/* radeon pitch is /64 */

	/* radeon pitch is /64 */

	size = num_pages << PAGE_SHIFT;

	size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;

	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);

	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);

	r = radeon_ring_lock(rdev, num_loops * 4 + 64);

	r = radeon_ring_lock(rdev, num_loops * 4 + 64);

	if (r) {

	if (r) {

drivers/gpu/drm/radeon/r600.c

+8 −6
Original line number Original line Diff line number Diff line
@@ -2209,7 +2209,8 @@ int r600_cp_resume(struct radeon_device *rdev) 
	/* Initialize the ring buffer's read and write pointers */

	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_RPTR_WR, 0);

	WREG32(CP_RB_RPTR_WR, 0);

	WREG32(CP_RB_WPTR, 0);

	rdev->cp.wptr = 0;

	WREG32(CP_RB_WPTR, rdev->cp.wptr);





	/* set the wb address whether it's enabled or not */

	/* set the wb address whether it's enabled or not */

	WREG32(CP_RB_RPTR_ADDR,

	WREG32(CP_RB_RPTR_ADDR,
@@ -2231,7 +2232,6 @@ int r600_cp_resume(struct radeon_device *rdev) 
	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));

	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));





	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	rdev->cp.wptr = RREG32(CP_RB_WPTR);





	r600_cp_start(rdev);

	r600_cp_start(rdev);

	rdev->cp.ready = true;

	rdev->cp.ready = true;
@@ -2353,21 +2353,23 @@ void r600_fence_ring_emit(struct radeon_device *rdev, 
}

}





int r600_copy_blit(struct radeon_device *rdev,

int r600_copy_blit(struct radeon_device *rdev,

		   uint64_t src_offset, uint64_t dst_offset,

		   uint64_t src_offset,

		   unsigned num_pages, struct radeon_fence *fence)

		   uint64_t dst_offset,

		   unsigned num_gpu_pages,

		   struct radeon_fence *fence)

{

{

	int r;

	int r;





	mutex_lock(&rdev->r600_blit.mutex);

	mutex_lock(&rdev->r600_blit.mutex);

	rdev->r600_blit.vb_ib = NULL;

	rdev->r600_blit.vb_ib = NULL;

	r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);

	r = r600_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);

	if (r) {

	if (r) {

		if (rdev->r600_blit.vb_ib)

		if (rdev->r600_blit.vb_ib)

			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

			radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);

		mutex_unlock(&rdev->r600_blit.mutex);

		mutex_unlock(&rdev->r600_blit.mutex);

		return r;

		return r;

	}

	}

	r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);

	r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);

	r600_blit_done_copy(rdev, fence);

	r600_blit_done_copy(rdev, fence);

	mutex_unlock(&rdev->r600_blit.mutex);

	mutex_unlock(&rdev->r600_blit.mutex);

	return 0;

	return 0;