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Commit 6d3f4120 authored by Harsh Sahu's avatar Harsh Sahu Committed by Gerrit - the friendly Code Review server
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drm/msm/gem: add cache flush api in msm_gem 



msm_gem object allocates the memory using kzalloc or vmalloc based on
memory size requirement. This is cacheable memory and must be flushed
before any cpu access on it. DSI and LUTDMA path does cpu access on this
memory while INLINE ROT and WB allows device access.
This change adds a sync api to ensure that cache is clean before device
does any DMA operation on the buffer.

Change-Id: I9c3e0fd4a05b66a041092c09f9719dc691664770
Signed-off-by: default avatarHarsh Sahu <hsahu@codeaurora.org>
parent 26082a82

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+1 −0
Original line number Diff line number Diff line
@@ -1076,6 +1076,7 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, 
		for (cnt = 0; cnt < length; cnt++)

			cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt];



		msm_gem_sync(dsi_ctrl->tx_cmd_buf);

		dsi_ctrl->cmd_len += length;



		if (!(msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) {

drivers/gpu/drm/msm/msm_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -724,6 +724,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 
void msm_gem_shrinker_init(struct drm_device *dev);

void msm_gem_shrinker_cleanup(struct drm_device *dev);



void msm_gem_sync(struct drm_gem_object *obj);

int msm_gem_mmap_obj(struct drm_gem_object *obj,

			struct vm_area_struct *vma);

int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);

drivers/gpu/drm/msm/msm_gem.c

+18 −0
Original line number Diff line number Diff line
@@ -163,6 +163,24 @@ void msm_gem_put_pages(struct drm_gem_object *obj) 
	/* when we start tracking the pin count, then do something here */

}



void msm_gem_sync(struct drm_gem_object *obj)

{

	struct msm_gem_object *msm_obj;



	if (!obj)

		return;



	msm_obj = to_msm_bo(obj);



	/*

	 * dma_sync_sg_for_device synchronises a single contiguous or

	 * scatter/gather mapping for the CPU and device.

	 */

	dma_sync_sg_for_device(obj->dev->dev, msm_obj->sgt->sgl,

		       msm_obj->sgt->nents, DMA_BIDIRECTIONAL);

}





int msm_gem_mmap_obj(struct drm_gem_object *obj,

		struct vm_area_struct *vma)

{

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1.c

+1 −0
Original line number Diff line number Diff line
@@ -526,6 +526,7 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg) 
	cmd1 |= (cfg->op == REG_DMA_WRITE) ? (BIT(22)) : 0;

	cmd1 |= (SIZE_DWORD(cfg->dma_buf->index) & MAX_DWORDS_SZ);



	msm_gem_sync(cfg->dma_buf->buf);

	SET_UP_REG_DMA_REG(hw, reg_dma);

	SDE_REG_WRITE(&hw, reg_dma_opmode_offset, BIT(0));

	val = SDE_REG_READ(&hw, reg_dma_intr_4_status_offset);