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Commit 6cdf01a5 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
Browse files

ASoC: Intel: cht_bsw_rt5645: cosmetic fixes 



Reorder variable names, change MCLK test, change quirks
No functional change

Suggested-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: default avatarLiam Girdwood <liam.r.girdwood@linux.intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 17b5273d

sound/soc/intel/boards/cht_bsw_rt5645.c

+35 −38
Original line number Diff line number Diff line
@@ -21,13 +21,13 @@ 
 */



#include <linux/module.h>

#include <linux/acpi.h>

#include <linux/platform_device.h>

#include <linux/acpi.h>

#include <linux/clk.h>

#include <linux/dmi.h>

#include <linux/slab.h>

#include <asm/cpu_device_id.h>

#include <asm/platform_sst_audio.h>

#include <linux/clk.h>

#include <sound/pcm.h>

#include <sound/pcm_params.h>

#include <sound/soc.h>
@@ -53,7 +53,7 @@ struct cht_mc_private { 
	struct clk *mclk;

};



#define CHT_RT5645_MAP(quirk)	((quirk) & 0xff)

#define CHT_RT5645_MAP(quirk)	((quirk) & GENMASK(7, 0))

#define CHT_RT5645_SSP2_AIF2     BIT(16) /* default is using AIF1  */

#define CHT_RT5645_SSP0_AIF1     BIT(17)

#define CHT_RT5645_SSP0_AIF2     BIT(18)
@@ -101,14 +101,12 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, 
	}



	if (SND_SOC_DAPM_EVENT_ON(event)) {

		if (ctx->mclk) {

		ret = clk_prepare_enable(ctx->mclk);

		if (ret < 0) {

			dev_err(card->dev,

				"could not configure MCLK state");

			return ret;

		}

		}

	} else {

		/* Set codec sysclk source to its internal clock because codec PLL will

		 * be off when idle and MCLK will also be off when codec is
@@ -122,7 +120,6 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, 
			return ret;

		}



		if (ctx->mclk)

		clk_disable_unprepare(ctx->mclk);

	}
@@ -258,11 +255,11 @@ static const struct dmi_system_id cht_rt5645_quirk_table[] = { 


static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)

{

	int ret;

	int jack_type;

	struct snd_soc_codec *codec = runtime->codec;

	struct snd_soc_card *card = runtime->card;

	struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);

	struct snd_soc_codec *codec = runtime->codec;

	int jack_type;

	int ret;



	if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||

	    (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
@@ -320,7 +317,7 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 


	rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack);



	if (ctx->mclk) {



	/*

	 * The firmware might enable the clock at

	 * boot (this information may or may not
@@ -339,7 +336,7 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 


	if (ret)

		dev_err(runtime->dev, "unable to set MCLK rate\n");

	}



	return ret;

}
@@ -545,15 +542,15 @@ struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */ 


static int snd_cht_mc_probe(struct platform_device *pdev)

{

	int ret_val = 0;

	int i;

	struct cht_mc_private *drv;

	struct snd_soc_card *card = snd_soc_cards[0].soc_card;

	struct sst_acpi_mach *mach;

	struct cht_mc_private *drv;

	const char *i2c_name = NULL;

	int dai_index = 0;

	bool found = false;

	bool is_bytcr = false;

	int dai_index = 0;

	int ret_val = 0;

	int i;



	drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC);

	if (!drv)
@@ -590,7 +587,7 @@ static int snd_cht_mc_probe(struct platform_device *pdev) 


	/* fixup codec name based on HID */

	i2c_name = sst_acpi_find_name_from_hid(mach->id);

	if (i2c_name != NULL) {

	if (i2c_name) {

		snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name),

			"%s%s", "i2c-", i2c_name);

		cht_dailink[dai_index].codec_name = cht_rt5645_codec_name;