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Commit 6cc6c16c authored by Tharun Kumar Merugu's avatar Tharun Kumar Merugu
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ARM: dts: msm: Add CDSP L3 node and Cx ipeak mitigation for ATOLL 



CDSP L3 devfreq node is needed for CDSP L3 governor to request
for L3 clock frequency based on application need on CDSP.
Cx ipeak mitigation framework enables communication between NPU and
CDSP drivers for Cx ipeak mitigation.

Change-Id: Ieb24fb0c0d8a0ab45651140fb1f5ec5d12cd84cc
Acked-by: default avatarSreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: default avatarTharun Kumar Merugu <mtharu@codeaurora.org>
parent 2b16b0cf

arch/arm64/boot/dts/qcom/atoll.dtsi

+14 −0
Original line number Original line Diff line number Diff line
@@ -1830,10 +1830,17 @@ 
				qcom,glink-channels = "cdsprmglink-apps-dsp";

				qcom,glink-channels = "cdsprmglink-apps-dsp";

				qcom,intents = <0x20 12>;

				qcom,intents = <0x20 12>;





				qcom,cdsp-cdsp-l3-gov {

					compatible = "qcom,cdsp-l3";

					qcom,target-dev = <&cdsp_cdsp_l3_lat>;

				};



				msm_cdsp_rm: qcom,msm_cdsp_rm {

				msm_cdsp_rm: qcom,msm_cdsp_rm {

					compatible = "qcom,msm-cdsp-rm";

					compatible = "qcom,msm-cdsp-rm";

					qcom,qos-latency-us = <44>;

					qcom,qos-latency-us = <44>;

					qcom,qos-maxhold-ms = <20>;

					qcom,qos-maxhold-ms = <20>;

					qcom,compute-cx-limit-en;

					qcom,compute-priority-mode = <2>;

					#cooling-cells = <2>;

					#cooling-cells = <2>;

				};

				};
@@ -2751,6 +2758,13 @@ 
			< 2400000 1459000000 >;

			< 2400000 1459000000 >;

	};

	};





	cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;

		governor = "powersave";

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		compatible = "qcom,devbw";

		governor = "performance";

		governor = "performance";