Loading Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ compatible: component name used for driver matching, should be one of the "qcom,jtag-fuse" for jtag fuse device "qcom,jtag-fuse-v2" for jtag fuse v2 device "qcom,jtag-fuse-v3" for jtag fuse v3 device "qcom,jtag-fuse-v4" for jtag fuse v4 device reg: physical base address and length of the register set reg-names: should be "fuse-base" Loading Documentation/devicetree/bindings/arm/msm/limits_lmh.txt 0 → 100644 +46 −0 Original line number Diff line number Diff line Limits Management Hardware Driver ================================ LMH driver provides API to interact with the LMH hardware. All the calls to the LMH hardware are routed via secure space. The device tree parameters for LMH driver are: Device/Asic specific properties: - reg : Base address of the LMH Lite hardware's interrupt status register and its size in bytes. 'reg' parameter is required if 'qcom,lmh-trim-err-offset' is set. - qcom,lmh-trim-err-offset : This property defines the bit in the LMH interrupt status register, which shows whether there is a trim error in LMH hardware. - vdd-apss-supply : This property should hold the phandle of APSS regulator. When defined, the M4M DPM will be notified for the APSS voltage change. - qcom,lmh-odcm-disable-threshold-mA : This property holds the APSS rail current threshold below which the ODCM will be disabled. This property requires the "vdd-apss-supply" property defined. Required parameters: - compatible: Must be either "qcom,lmh" or "qcom,lmh_v1". The driver based on the compatible string will decide the default profile. - interrupts: LMH Lite hardware interrupt details. Example: qcom,lmh { compatible = "qcom,lmh"; interrupts = <0 332 4>; reg = <0xF9117000 0x4>; qcom,lmh-trim-err-offset = <18>; vdd-apss-supply = <&pm8994_s11>; qcom,lmh-odcm-disable-threshold-mA = <850>; }; Or for asics that don't have trim err and don't require the voltage change update for DPM. qcom,lmh { compatible = "qcom,lmh_v1"; interrupts = <0 332 4>; }; Documentation/devicetree/bindings/arm/msm/msm.txt +1 −0 Original line number Diff line number Diff line Loading @@ -257,3 +257,4 @@ compatible = "qcom,mdm9607-mtp" compatible = "qcom,sdm660-cdp" compatible = "qcom,sdm660-mtp" compatible = "qcom,sdm660-qrd" compatible = "qcom,sdm660-sim" Documentation/devicetree/bindings/arm/msm/msm_core.txt 0 → 100644 +71 −0 Original line number Diff line number Diff line MSM Core Energy Aware driver The Energy Aware driver provides per core power and temperature information to the scheduler for it to make more power efficient scheduling decision. The required properties for the Energy-aware driver are: - compatible: "qcom,apss-core-ea" - reg: Physical address mapped to this device Required nodes: - ea@X: Parent node that has the sensor mapping for each cpu. This node's phandle is provided within cpu node to invoke/probe energy-aware only for available cpus. There should be one such node present for each cpu. Optional properties: - qcom,low-hyst-temp: Degrees C below which the power numbers need to be recomputed for the cores and reset the threshold. If this is not present, the default value is 10C. - qcom,high-hyst-temp: Degrees C above which the power numbers need to be recomputed for the cores and reset the threshold. If this property is not present, the default value is 5C. - qcom,polling-interval: Interval for which the power numbers need to be recomputed for the cores if there is no change in threshold. If this property is not present, the power is recalculated only on temperature threshold notifications. -qcom,throttling-temp: Temperature threshold for cpu frequency mitigation. The value should be set same as the threshold temperature in thermal module - 5 C, such that there is a bandwidth to control the cores before frequency mitigation happens. [Second level nodes] Require properties to define per core characteristics: - sensor: Sensor phandle to map a particular sensor to the core. If this property is not present, then the core is assumed to be at 40C for all the power estimations. No sensor threshold is set. This phandle's compatible property is "qcom,sensor-information". This driver relies on the sensor-type and scaling-factor information provided in this phandle. Example qcom,msm-core@0xfc4b0000 { compatible = "qcom,apss-core-ea"; reg = <0xfc4b0000 0x1000>; qcom,low-hyst-temp = <10>; qcom,high-hyst-temp = <5>; qcom,polling-interval = <50>; ea0: ea0 { sensor = <&sensor_information0>; }; ea1: ea1 { sensor = <&sensor_information1>; }; }; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; qcom,ea = <&ea0>; }; Documentation/devicetree/bindings/arm/msm/system_stats.txt 0 → 100644 +93 −0 Original line number Diff line number Diff line * System sleep stats Resource Power manager maintains information about system sleep and the time each master spent in respective sleep modes. These were previously exported through two modules, one for system and another for the respective master votes. The two modules are now combined into a system stats drivers to provide better visibility into system sleep modes. Main node properties - compatible Usage: Required Value type: <string> Definition: must be "qcom,system-stats". - qcom,rpm-msg-ram Usage: Required Value type: <phandle> Definition: phandle to RPM's message ram registers. - qcom,rpm-code-ram Usage: Required Value type: <phandle> Definition: phandle to RPM's code ram registers. - qcom,masters: Usage: Required Value type: <string list> Definition of memory DT phandles that system stats module is dependent on. qcom,rpm-msg-ram: The required phandle pointed to by qcom,rpm-msg-ram are: Node properties: - compatible: Usage: Required Value Type: <string> Definition: must be "qcom,rpm-msg-ram" - reg: Usage: Required Value Type: <prop-encoded-array> Definition: Addresses and sizes for RPM address as visible to Apps and Stats address location. - reg-names: Usage: Required Value Type: <stringlist> Definition: Address names. Must be "phys_addr_base" or "msg-ram-base". Must be specified in the same order as the corresponding addresses in the reg property. qcom,rpm-code-ram: The required phandle pointed to by qcom,rpm-msg-ram are: Node properties: - compatible: Usage: Required Value Type: <string> Definition: must be "qcom,rpm-code-ram". - reg: Usage: Required Value Type: <prop-encoded-array> Definition: Address and size for RPM code address. - reg-names: Usage: Required Value Type: <stringlist> Definition: Address names. Must be "msg-ram-base" Example: rpm_code_ram: rpm-memory@0x68000 { compatible = "qcom,rpm-code-ram"; reg = <0x68000 0x5000>; reg-name = "msg-ram-base"; }; rpm_msg_ram: memory@0x200000 { compatible = "qcom,rpm-msg-ram"; reg = <0x200000 0x1000>, <0x290000 0x1000>; reg-names = "phys_addr_base", "code-ram-base"; }; qcom,system-stats@68140 { compatible = "qcom,system-stats"; qcom,rpm-msg-ram = <&rpm_msg_ram>; qcom,rpm-code-ram = <&rpm_code_ram>; qcom,masters = "APSS", "MPSS", "ADSP", "SLPI"; }; Loading
Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ compatible: component name used for driver matching, should be one of the "qcom,jtag-fuse" for jtag fuse device "qcom,jtag-fuse-v2" for jtag fuse v2 device "qcom,jtag-fuse-v3" for jtag fuse v3 device "qcom,jtag-fuse-v4" for jtag fuse v4 device reg: physical base address and length of the register set reg-names: should be "fuse-base" Loading
Documentation/devicetree/bindings/arm/msm/limits_lmh.txt 0 → 100644 +46 −0 Original line number Diff line number Diff line Limits Management Hardware Driver ================================ LMH driver provides API to interact with the LMH hardware. All the calls to the LMH hardware are routed via secure space. The device tree parameters for LMH driver are: Device/Asic specific properties: - reg : Base address of the LMH Lite hardware's interrupt status register and its size in bytes. 'reg' parameter is required if 'qcom,lmh-trim-err-offset' is set. - qcom,lmh-trim-err-offset : This property defines the bit in the LMH interrupt status register, which shows whether there is a trim error in LMH hardware. - vdd-apss-supply : This property should hold the phandle of APSS regulator. When defined, the M4M DPM will be notified for the APSS voltage change. - qcom,lmh-odcm-disable-threshold-mA : This property holds the APSS rail current threshold below which the ODCM will be disabled. This property requires the "vdd-apss-supply" property defined. Required parameters: - compatible: Must be either "qcom,lmh" or "qcom,lmh_v1". The driver based on the compatible string will decide the default profile. - interrupts: LMH Lite hardware interrupt details. Example: qcom,lmh { compatible = "qcom,lmh"; interrupts = <0 332 4>; reg = <0xF9117000 0x4>; qcom,lmh-trim-err-offset = <18>; vdd-apss-supply = <&pm8994_s11>; qcom,lmh-odcm-disable-threshold-mA = <850>; }; Or for asics that don't have trim err and don't require the voltage change update for DPM. qcom,lmh { compatible = "qcom,lmh_v1"; interrupts = <0 332 4>; };
Documentation/devicetree/bindings/arm/msm/msm.txt +1 −0 Original line number Diff line number Diff line Loading @@ -257,3 +257,4 @@ compatible = "qcom,mdm9607-mtp" compatible = "qcom,sdm660-cdp" compatible = "qcom,sdm660-mtp" compatible = "qcom,sdm660-qrd" compatible = "qcom,sdm660-sim"
Documentation/devicetree/bindings/arm/msm/msm_core.txt 0 → 100644 +71 −0 Original line number Diff line number Diff line MSM Core Energy Aware driver The Energy Aware driver provides per core power and temperature information to the scheduler for it to make more power efficient scheduling decision. The required properties for the Energy-aware driver are: - compatible: "qcom,apss-core-ea" - reg: Physical address mapped to this device Required nodes: - ea@X: Parent node that has the sensor mapping for each cpu. This node's phandle is provided within cpu node to invoke/probe energy-aware only for available cpus. There should be one such node present for each cpu. Optional properties: - qcom,low-hyst-temp: Degrees C below which the power numbers need to be recomputed for the cores and reset the threshold. If this is not present, the default value is 10C. - qcom,high-hyst-temp: Degrees C above which the power numbers need to be recomputed for the cores and reset the threshold. If this property is not present, the default value is 5C. - qcom,polling-interval: Interval for which the power numbers need to be recomputed for the cores if there is no change in threshold. If this property is not present, the power is recalculated only on temperature threshold notifications. -qcom,throttling-temp: Temperature threshold for cpu frequency mitigation. The value should be set same as the threshold temperature in thermal module - 5 C, such that there is a bandwidth to control the cores before frequency mitigation happens. [Second level nodes] Require properties to define per core characteristics: - sensor: Sensor phandle to map a particular sensor to the core. If this property is not present, then the core is assumed to be at 40C for all the power estimations. No sensor threshold is set. This phandle's compatible property is "qcom,sensor-information". This driver relies on the sensor-type and scaling-factor information provided in this phandle. Example qcom,msm-core@0xfc4b0000 { compatible = "qcom,apss-core-ea"; reg = <0xfc4b0000 0x1000>; qcom,low-hyst-temp = <10>; qcom,high-hyst-temp = <5>; qcom,polling-interval = <50>; ea0: ea0 { sensor = <&sensor_information0>; }; ea1: ea1 { sensor = <&sensor_information1>; }; }; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; qcom,ea = <&ea0>; };
Documentation/devicetree/bindings/arm/msm/system_stats.txt 0 → 100644 +93 −0 Original line number Diff line number Diff line * System sleep stats Resource Power manager maintains information about system sleep and the time each master spent in respective sleep modes. These were previously exported through two modules, one for system and another for the respective master votes. The two modules are now combined into a system stats drivers to provide better visibility into system sleep modes. Main node properties - compatible Usage: Required Value type: <string> Definition: must be "qcom,system-stats". - qcom,rpm-msg-ram Usage: Required Value type: <phandle> Definition: phandle to RPM's message ram registers. - qcom,rpm-code-ram Usage: Required Value type: <phandle> Definition: phandle to RPM's code ram registers. - qcom,masters: Usage: Required Value type: <string list> Definition of memory DT phandles that system stats module is dependent on. qcom,rpm-msg-ram: The required phandle pointed to by qcom,rpm-msg-ram are: Node properties: - compatible: Usage: Required Value Type: <string> Definition: must be "qcom,rpm-msg-ram" - reg: Usage: Required Value Type: <prop-encoded-array> Definition: Addresses and sizes for RPM address as visible to Apps and Stats address location. - reg-names: Usage: Required Value Type: <stringlist> Definition: Address names. Must be "phys_addr_base" or "msg-ram-base". Must be specified in the same order as the corresponding addresses in the reg property. qcom,rpm-code-ram: The required phandle pointed to by qcom,rpm-msg-ram are: Node properties: - compatible: Usage: Required Value Type: <string> Definition: must be "qcom,rpm-code-ram". - reg: Usage: Required Value Type: <prop-encoded-array> Definition: Address and size for RPM code address. - reg-names: Usage: Required Value Type: <stringlist> Definition: Address names. Must be "msg-ram-base" Example: rpm_code_ram: rpm-memory@0x68000 { compatible = "qcom,rpm-code-ram"; reg = <0x68000 0x5000>; reg-name = "msg-ram-base"; }; rpm_msg_ram: memory@0x200000 { compatible = "qcom,rpm-msg-ram"; reg = <0x200000 0x1000>, <0x290000 0x1000>; reg-names = "phys_addr_base", "code-ram-base"; }; qcom,system-stats@68140 { compatible = "qcom,system-stats"; qcom,rpm-msg-ram = <&rpm_msg_ram>; qcom,rpm-code-ram = <&rpm_code_ram>; qcom,masters = "APSS", "MPSS", "ADSP", "SLPI"; };
