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Commit 6bce431c authored by Yuvaraj Kumar C D's avatar Yuvaraj Kumar C D Committed by Chris Ball
Browse files

mmc: dw_mmc: exynos: configure SMU in exynos5420 



Exynos5420 Mobile Storage Host controller has Security Management
Unit (SMU) for channel 0 and channel 1 (mainly for eMMC).
This time, SMU configuration is set for non-encryption mode.

Signed-off-by: default avatarYuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Tested-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Acked-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent 002f0d5c

drivers/mmc/host/dw_mmc-exynos.c

+37 −1
Original line number Diff line number Diff line
@@ -35,12 +35,32 @@ 
#define EXYNOS4210_FIXED_CIU_CLK_DIV	2

#define EXYNOS4412_FIXED_CIU_CLK_DIV	4



/* Block number in eMMC */

#define DWMCI_BLOCK_NUM		0xFFFFFFFF



#define SDMMC_EMMCP_BASE	0x1000

#define SDMMC_MPSECURITY	(SDMMC_EMMCP_BASE + 0x0010)

#define SDMMC_MPSBEGIN0		(SDMMC_EMMCP_BASE + 0x0200)

#define SDMMC_MPSEND0		(SDMMC_EMMCP_BASE + 0x0204)

#define SDMMC_MPSCTRL0		(SDMMC_EMMCP_BASE + 0x020C)



/* SMU control bits */

#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)

#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)

#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)

#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)

#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)

#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)

#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)

#define DWMCI_MPSCTRL_VALID			BIT(0)



/* Variations in Exynos specific dw-mshc controller */

enum dw_mci_exynos_type {

	DW_MCI_TYPE_EXYNOS4210,

	DW_MCI_TYPE_EXYNOS4412,

	DW_MCI_TYPE_EXYNOS5250,

	DW_MCI_TYPE_EXYNOS5420,

	DW_MCI_TYPE_EXYNOS5420_SMU,

};



/* Exynos implementation specific driver private data */
@@ -67,6 +87,9 @@ static struct dw_mci_exynos_compatible { 
	}, {

		.compatible	= "samsung,exynos5420-dw-mshc",

		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420,

	}, {

		.compatible	= "samsung,exynos5420-dw-mshc-smu",

		.ctrl_type	= DW_MCI_TYPE_EXYNOS5420_SMU,

	},

};
@@ -74,6 +97,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) 
{

	struct dw_mci_exynos_priv_data *priv = host->priv;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {

		mci_writel(host, MPSBEGIN0, 0);

		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);

		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |

			   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |

			   DWMCI_MPSCTRL_VALID |

			   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);

	}



	return 0;

}
@@ -82,7 +114,8 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) 
	struct dw_mci_exynos_priv_data *priv = host->priv;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)

	    priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 ||

	    priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU)

		host->bus_hz /= (priv->ciu_div + 1);

	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)

		host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
@@ -104,6 +137,7 @@ static int dw_mci_exynos_resume(struct device *dev) 
{

	struct dw_mci *host = dev_get_drvdata(dev);



	dw_mci_exynos_priv_init(host);

	return dw_mci_resume(host);

}
@@ -222,6 +256,8 @@ static const struct of_device_id dw_mci_exynos_match[] = { 
			.data = &exynos_drv_data, },

	{ .compatible = "samsung,exynos5420-dw-mshc",

			.data = &exynos_drv_data, },

	{ .compatible = "samsung,exynos5420-dw-mshc-smu",

			.data = &exynos_drv_data, },

	{},

};

MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);