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Commit 6abae13f authored by Junzhe Zou's avatar Junzhe Zou
Browse files

msm: camera: ife: config rdi HFR 



Since RDI path doesn't have address increment register,
config address manually to support rdi HFR mode.

Change-Id: Ida7dd4d6840f48d08d6adaacff56cde25b0bd48c
Signed-off-by: default avatarJunzhe Zou <jnzhezou@codeaurora.org>
parent f6d7fcbe

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c

+31 −15
Original line number Diff line number Diff line
@@ -2692,8 +2692,9 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
	struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL;

	struct cam_vfe_bus_ver2_reg_offset_ubwc_client *ubwc_client = NULL;

	uint32_t *reg_val_pair;

	uint32_t  i, j, size = 0;

	uint32_t  i, j, k, size = 0;

	uint32_t  frame_inc = 0, val;

	uint32_t loop_size = 0;



	bus_priv = (struct cam_vfe_bus_ver2_priv  *) priv;

	update_buf =  (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -2776,20 +2777,6 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
				update_buf->wm_update->image_buf[i]);

		}



		/* WM Image address */

		if (wm_data->en_ubwc)

			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

				wm_data->hw_regs->image_addr,

				(update_buf->wm_update->image_buf[i] +

				io_cfg->planes[i].meta_size));

		else

			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

				wm_data->hw_regs->image_addr,

				update_buf->wm_update->image_buf[i] +

				wm_data->offset);

		CAM_DBG(CAM_ISP, "WM %d image address 0x%x",

			wm_data->index, reg_val_pair[j-1]);



		if (wm_data->en_ubwc) {

			frame_inc = ALIGNUP(io_cfg->planes[i].plane_stride *

			    io_cfg->planes[i].slice_height, 4096);
@@ -2805,6 +2792,28 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, 
				io_cfg->planes[i].slice_height;

		}



		if (wm_data->index < 3)

			loop_size = wm_data->irq_subsample_period + 1;

		else

			loop_size = 1;



		/* WM Image address */

		for (k = 0; k < loop_size; k++) {

			if (wm_data->en_ubwc)

				CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

					wm_data->hw_regs->image_addr,

					update_buf->wm_update->image_buf[i] +

					io_cfg->planes[i].meta_size +

					k * frame_inc);

			else

				CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

					wm_data->hw_regs->image_addr,

					update_buf->wm_update->image_buf[i] +

					wm_data->offset + k * frame_inc);

			CAM_DBG(CAM_ISP, "WM %d image address 0x%x",

				wm_data->index, reg_val_pair[j-1]);

		}



		CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

			wm_data->hw_regs->frame_inc, frame_inc);

		CAM_DBG(CAM_ISP, "WM %d frame_inc %d",
@@ -2875,6 +2884,13 @@ static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, 


		wm_data = vfe_out_data->wm_res[i]->res_priv;



		if (wm_data->index <= 2 && hfr_cfg->subsample_period > 3) {

			CAM_ERR(CAM_ISP,

				"RDI doesn't support irq subsample period %d",

				hfr_cfg->subsample_period);

			return -EINVAL;

		}



		if ((wm_data->framedrop_pattern !=

			hfr_cfg->framedrop_pattern) ||

			!wm_data->hfr_cfg_done) {